Long-Grain Metallic Interconnects via Selective Silicidation
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Solution Overview
Problem
Back-end-of-line (BEOL) interconnects in integrated circuits have relatively short crystalline grains, leading to high electrical resistance due to grain boundary scattering, and existing methods to extend grain length are ineffective at ultra-scaled line widths.
Innovation Solution
A method involving forming an interconnect layout with a non-diffusing material, a diffusing barrier layer, and a diffusing layer, where the diffusing layer is thermally reacted to chemically diffuse and grow crystalline grains along the interconnect lines, reducing electrical resistance by forming longer crystalline grains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional continuous metal layer formation is used, then manufacturing is simple, but crystalline grain length is short leading to high electrical resistance
Solution Approach 1:
The continuous metal layer is segmented into discrete metallic islands formed through selective silicidation at specific nucleation sites. This segmentation allows control over grain growth initiation points, enabling longer crystalline grains to form between nucleation sites rather than throughout the entire continuous layer, thereby reducing electrical resistance while managing process complexity.
Solution Approach 2:
Nucleation sites are pre-formed on the semiconductor substrate before metal layer deposition. These pre-formed nucleation sites serve as controlled initiation points for crystalline grain growth, ensuring that grains grow from predetermined locations rather than forming randomly throughout the metal layer, which enables longer grain lengths and lower resistance.
2Length of stationary object
If liner engineering or recrystallization anneal methods are used, then crystalline grain length increases, but electrical line resistance remains large at ultra-scaled line widths
Solution Approach 1:
The metal layer is selectively silicidized at specific local regions (nucleation sites) rather than uniformly throughout. This local treatment creates controlled grain growth initiation points while leaving other regions unaffected, allowing grains to grow longer between nucleation sites without the need for global liner engineering or recrystallization annealing, thereby achieving both longer grains and lower resistance at ultra-scaled dimensions.
Solution Approach 2:
The silicidation process parameters (temperature, time, metal layer thickness) are specifically optimized to control the extent of material diffusion and grain growth. By adjusting these parameters, the method achieves complete or partial metal layer consumption, which directly controls crystalline grain length and electrical resistance without requiring additional liner engineering steps or high-temperature recrystallization annealing.
3Reliability
If complete silicidation is performed, then metallic interconnects are fully formed, but control over grain structure becomes limited
Solution Approach 1:
Nucleation sites are pre-formed with specific geometries and materials before metal layer deposition. These pre-configured nucleation sites control where and how grain growth initiates, providing manufacturing precision over grain structure while still achieving complete silicidation of the metal layer. The nucleation site design (material composition, thickness, pattern) directly influences the resulting grain structure.
Solution Approach 2:
The silicidation process parameters are precisely controlled to achieve the desired balance between complete metal layer consumption and grain structure control. By adjusting metal layer thickness, silicidation temperature, and time, the method achieves complete silicidation while maintaining control over grain length and structure through the pre-formed nucleation sites.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces electrical resistance in interconnects by growing longer crystalline grains, improving performance at ultra-scaled line widths compared to traditional methods.
Implementation Method 1
thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line
Implementation Method 2
causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portion of the diffusing layer and the portion of the at least one line
Implementation Method 3
at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface
Implementation Method 4
Thermally reacting the diffusing layer may silicidize the at least one line
Data Source
AI summary
A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.