Long Transaction Execution via Deferred Store Commit

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Solution Overview

Problem

Existing synchronization mechanisms, such as mutual-exclusion locking, can lead to deadlocks, excessive latency, and priority inversion in systems with limited transactional hardware resources, making it challenging to execute long transactions efficiently.

Innovation Solution

A system that executes long transactions in a non-transactional mode, deferring stores to a thread-specific commit buffer and committing them using multiple hardware transactions or multi-word compare and swap operations, allowing for lock-free execution and parallelism without relying on transactional hardware resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hardware transactional memory is used to execute transactions, then lock-freedom and increased parallelism are achieved, but the system is limited by finite transactional hardware resources and cannot support large transactions

Engineering Contradiction:
Improvesystem throughputVSAvoidtransaction size support
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments a long transaction into multiple short hardware transactions. Each short transaction processes a subset of the deferred stores within the hardware transaction resource limits. The system divides the workload across multiple transactions that are orchestrated to achieve the overall effect of the long transaction, thereby supporting large-scale operations within constrained hardware resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by deferring stores during the execution of the long transaction body without immediately committing them to the architectural state. This allows the transaction to accumulate all necessary store operations first, then commit them atomically at the end using multiple short hardware transactions, enabling long transactions to exceed individual hardware transaction limits.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If mutual-exclusion locking is used to protect critical sections, then atomicity is ensured, but deadlocks, excessive latency, and priority inversion occur

Engineering Contradiction:
Improveatomicity guaranteeVSAvoidlock acquisition latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the mechanical mutual-exclusion locking mechanism with a software transactional memory approach using deferred stores and atomic commit operations. Instead of using locks that require thread blocking and potential deadlocks, the system uses a lock-free deferred store mechanism where multiple threads can execute concurrently and commit their stores atomically at the end, eliminating lock acquisition latency and deadlock risks while maintaining atomicity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If a thread is stalled or preempted while executing a critical section under mutual exclusion, then other threads are blocked, but this causes excessive latency and priority inversion

Engineering Contradiction:
Improvecritical section protectionVSAvoidthread throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces deferred stores as an intermediary mechanism between thread execution and memory commitment. Instead of directly committing stores to memory during critical section execution (which blocks other threads), the system buffers stores in a deferred store structure and commits them atomically at the end. This intermediary allows concurrent thread execution without blocking, improving throughput while maintaining critical section protection through the atomic commit operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7669040B2Method and apparatus for executing a long transaction
Publication Date: 2010.02.23 ORACLE AMERICAN INC
  • US7669040B2 patent drawing
  • US7669040B2 patent drawing
  • US7669040B2 patent drawing

AI summary

A system that executes a long transaction in a system with limited transactional hardware resources. During operation, the system executes the long transaction in a non transactional mode, which does not use transactional hardware resources. The system defers stores generated during the long transaction so that the stores are not committed to the architectural state of a processor until the transaction is successfully completed. If the long transaction successfully completes, the system commits the long transaction, which involves performing multiple hardware transactions to commit the deferred stores to the architectural state of the processor.