Look-Ahead ECC Encoding for NV Memory Write Delay Elimination

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Solution Overview

Problem

Existing memory devices face challenges with encoding delays and data vacancies during error correction code processing in MLC flash memories, leading to complexities in circuit architecture and performance issues.

Innovation Solution

A non-volatile memory accessing method using look-ahead processing for data protection, where the memory controller generates parity codes through look-ahead type encoding, allowing for simultaneous encoding and data transfer without delays, thereby simplifying the circuit architecture and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional encoding methods are used in MLC flash memory, then data protection is achieved, but encoding delays occur and circuit architecture becomes complex

Engineering Contradiction:
Improvedata protectionVSAvoidencoding delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing look-ahead encoding that anticipates future data arrivals. The encoding circuit starts processing parity codes for current data while simultaneously receiving and buffering next data, so that encoding is already in progress before the next data block arrives, eliminating idle waiting time and encoding delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by ensuring the encoding circuit operates continuously without idle periods. Through look-ahead processing and data buffering, the encoder maintains an uninterrupted workflow where encoding of current data and reception of next data overlap, maximizing resource utilization and eliminating vacancies in the data transfer path.

Inventive Principle:
Principle #20Continuity of useful action

2Reliability

If traditional encoding methods are used in MLC flash memory, then data protection is achieved, but circuit architecture becomes complicated

Engineering Contradiction:
Improvedata protectionVSAvoidcircuit architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the encoding process into distinct functional modules: a look-ahead encoding circuit that processes current data, a buffer that stores incoming data, and a controller that coordinates operations. This modular segmentation allows each component to perform its function independently, simplifying the overall circuit architecture while maintaining robust data protection capabilities.

Inventive Principle:
Principle #1Segmentation

3Loss of time

If look-ahead processing is implemented, then encoding delays are eliminated, but data transfer path vacancies may occur

Engineering Contradiction:
Improveencoding delayVSAvoiddata transfer efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent applies dynamics by implementing adaptive control of the data transfer process. The controller dynamically adjusts the timing and flow of data based on the encoding status and buffer conditions, optimizing the balance between look-ahead encoding benefits and maintaining continuous data flow, thereby preventing vacancies while eliminating delays.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10866859B1Non-volatile memory accessing method using data protection with aid of look-ahead processing, and associated apparatus
Publication Date: 2020.12.15 SILICON MOTION INC
  • US10866859B1 patent drawing
  • US10866859B1 patent drawing
  • US10866859B1 patent drawing

AI summary

A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.