Look Ahead Normaliser Parallel OR-Reduction Logic
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Solution Overview
Problem
Existing normalizers and renormalizers in floating point units face inefficiencies in the normalization process, particularly in terms of speed and critical path delay, due to sequential execution of OR-reduction and left shifting operations.
Innovation Solution
The proposed solution involves a look ahead normalizer architecture that employs a series of hardware logic stages with left shifting and OR-reduction logic elements. Each stage performs OR-reduction on different subsets of bits and left shifting based on the OR-reduction results, allowing for parallel execution and reducing critical path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential execution of OR-reduction and left shifting operations is used, then device complexity is reduced, but speed and critical path delay worsen
Solution Approach 1:
The patent applies preliminary action by performing OR-reduction operations on different subsets of bits in advance before the left shifting operation. Multiple OR-reduction logic elements process different bit subsets simultaneously and prepare their results beforehand, so that when the left shifting operation needs to occur, the reduction results are already available. This eliminates the sequential dependency where left shifting must wait for OR-reduction to complete, thereby reducing critical path delay and improving normalization speed without significantly increasing device complexity.
2Ease of operation
If sequential execution of OR-reduction and left shifting operations is used, then ease of operation is maintained, but productivity worsens
Solution Approach 1:
The patent applies segmentation by dividing the input binary number into different subsets of bits and assigning each subset to a separate OR-reduction logic element. These segmented bit subsets are processed in parallel across multiple logic elements simultaneously, rather than processing all bits sequentially through a single OR-reduction operation. This segmentation enables concurrent processing of multiple bit groups, significantly improving normalization throughput and productivity while maintaining ease of operation through the systematic organization of parallel processing stages.
3Speed
If parallel execution of OR-reduction and left shifting operations is enabled, then speed and critical path delay improve, but device complexity increases
Solution Approach 1:
The patent applies merging by combining multiple OR-reduction logic elements and left shifting logic elements into an integrated parallel processing architecture. The OR-reduction results from different logic elements are merged and combined to control the left shifting operation simultaneously. This merging of multiple parallel processing paths into a unified normalizer structure enables speed improvement through parallel execution while managing device complexity through systematic integration of the parallel components into a cohesive hardware design.
Data Source
AI summary
Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.