Look-Ahead Rank Switching Circuit for Shared IO Reference Voltages
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Solution Overview
Problem
In multi-rank circuit systems, the conventional approach to generating reference voltages for pseudo-differential signaling interfaces requires numerous reference voltage generators and control signals, leading to significant circuit area consumption, layout complexity, and power inefficiencies, particularly in high-density systems where fast rank switching is hindered by the settling time of analog reference voltages.
Innovation Solution
A global reference voltage generator provides a range of voltages to local reference voltage generators, reducing the number of control signals and circuit area by allowing each local generator to transform these voltages into pin-specific reference voltages, and implementing a unified receiver with digital control of transistor strength for fine-tuning, enabling faster rank switching and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple per-pin reference voltage generators are implemented for each rank, then optimal reference voltage can be provided for each receiver, but circuit area consumption increases substantially
Solution Approach 1:
The reference voltage generation system is segmented into a single global reference voltage generator that serves all receivers, eliminating the need for multiple per-pin generators. This segmentation reduces circuit area while maintaining reference voltage precision through shared generation resources.
Solution Approach 2:
The global reference voltage generator is designed to serve multiple receivers universally, providing reference voltages to all pins across all ranks. This multi-functional approach replaces numerous specialized per-pin generators, significantly reducing circuit area while maintaining optimal reference voltage provision for each receiver.
2Measurement precision
If per-pin reference voltage generators are co-located near their respective pins, then optimal reference voltage can be provided, but layout complexity and routing complexity increase
Solution Approach 1:
The reference voltage generation function is extracted from the crowded pin vicinity and consolidated into a single global generator located in a less congested area of the circuit. This extraction removes the burden of co-locating multiple generators near pins, simplifying layout while maintaining reference voltage precision through the global generator's centralized design.
3Measurement precision
If multiple per-pin reference voltage generators are implemented, then each receiver can be optimized, but the number of control signals increases substantially
Solution Approach 1:
Multiple per-pin control signals are merged into a single set of control signals that manage the global reference voltage generator. This consolidation reduces control signal complexity from hundreds of individual signals to a manageable number of global control signals while maintaining reference voltage precision through unified management.
4Adaptability or versatility
If analog reference voltage is switched when ranks are switched, then reference voltage can be changed for different ranks, but settling time prevents fast rank switching
Solution Approach 1:
The global reference voltage generator is pre-configured with rank-specific reference voltage values stored in lookup tables or configuration memory. When rank switching is required, the generator quickly retrieves and switches to the pre-prepared reference voltage for the target rank, eliminating the settling time associated with generating new analog voltages. This preliminary preparation enables fast rank switching while maintaining adaptability to different ranks.
Data Source
AI summary
A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.