Lookup Circuit Hash Function Evaluation for Low Latency
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Solution Overview
Problem
Existing hardware implementations of lookup tables for network applications face challenges in achieving low latency and high memory capacity while managing power consumption and key size limitations, and software approaches lack efficiency in parallel processing.
Innovation Solution
The implementation of programmable hash tables with hardware circuitry that evaluates hash functions to map keys to addresses in memory, using sparse bit matrices and pre-computed hash functions to reduce latency and identify suitable pairs of hash functions for efficient lookup operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If TCAMs are used for lookup tables, then access latency is reduced, but memory capacity and power efficiency deteriorate
Solution Approach 1:
The patent divides the lookup table into multiple segments stored in standard SRAM, organized in a tree structure where each level contains a portion of the key-space. This segmentation allows the system to achieve high capacity using standard SRAM while maintaining low latency through parallel evaluation of hash functions at different tree levels.
Solution Approach 2:
The patent replaces the specialized TCAM hardware mechanism with a combination of standard SRAM and programmable hash function evaluation circuits. This substitution uses software-generated hash functions implemented in hardware to achieve TCAM-like performance with SRAM's advantages in capacity and power efficiency.
2Loss of time
If TCAMs are used for lookup tables, then access latency is reduced, but power consumption increases
Solution Approach 1:
The patent substitutes power-hungry TCAM hardware with standard SRAM combined with hash function evaluation circuits. Standard SRAM consumes significantly less power per bit than TCAM, and the hash function circuits are designed to be energy-efficient, achieving low latency without the high power consumption of TCAM.
Solution Approach 2:
The patent changes the fundamental operating parameters of the lookup table by using SRAM's volatile memory characteristics combined with pre-computed hash functions. This parameter change allows the system to achieve deterministic low latency through hardware acceleration of hash evaluation while maintaining the low power density inherent to SRAM technology.
3Quantity of substance
If standard SRAM with tree-based structures is used, then memory capacity increases, but access latency increases due to multiple memory accesses
Solution Approach 1:
The patent performs preliminary computation of hash functions during the table construction phase, generating hash values for all possible keys at each tree level. These pre-computed hash values are stored in the SRAM alongside the key-data pairs, enabling the lookup circuit to directly evaluate hashes during access without sequential traversal, thereby reducing latency while maintaining high capacity.
4Adaptability or versatility
If software hash table approaches are used, then flexibility in key sizes and table configurations improves, but parallel processing efficiency deteriorates
Solution Approach 1:
The patent substitutes software-based hash table management with hardware-implemented hash function evaluation circuits that operate in parallel. The flexibility of software approaches is preserved through programmable hash function generators, while parallel processing efficiency is achieved through concurrent evaluation of multiple hash functions in hardware logic.
Solution Approach 2:
The patent creates a universal hardware architecture that can handle variable key sizes and different table configurations through programmable hash function generators. The same hardware circuit can be configured to evaluate different hash functions for different key formats, providing software-like flexibility with hardware-speed parallel processing capability.
Data Source
AI summary
A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit includes multiple hash function sub-circuits, each of which applies a respective hash function to an input key, producing a hash value. Candidate pairs of hash functions to be implemented by the hash function sub-circuits may be generated and tested for suitability in hashing a particular collection of keys. The suitability testing may include computing hash value bit vectors by applying each hash function in a candidate pair to a given key, and determining (using a modified union-find type operation that organizes objects in each set as a directed graph whose root points to itself) whether the resulting hash value bit vectors belong to the same set. The union-find type operation may include a limited distance-from-root test, path compression, or exception handling for special cases, but not a rank test.