Low-Latency Lookup Circuit Using Programmable Hash Tables
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Solution Overview
Problem
Existing hardware implementations of lookup tables for network applications face challenges in achieving low-latency, high-throughput key lookups with variable key and data sizes, while maintaining efficient memory utilization, due to limitations in existing CAMs and SRAM-based solutions.
Innovation Solution
The implementation of programmable hash tables using hardware circuitry that evaluates hash functions to map keys to addresses in memory, allowing for efficient construction of lookup tables with pre-computed hash functions and flexible key sizes, enabling low-latency access and efficient memory utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If TCAMs are used for fast lookup, then access latency is reduced, but memory capacity is limited and power consumption increases
Solution Approach 1:
The patent merges SRAM-based storage with custom hash function hardware circuits to create a hybrid lookup system. The SRAM provides high-capacity storage while the dedicated hash circuits perform fast hashing in parallel, combining the advantages of both approaches to achieve both high capacity and low latency without the power consumption issues of TCAMs.
Solution Approach 2:
The patent replaces the mechanical/comparative system of TCAMs with a computational hashing system using SRAM and custom hash circuits. Instead of comparing keys directly in parallel as TCAMs do, the system computes hash values through dedicated hardware circuits that operate on SRAM data, achieving faster lookup with better capacity and lower power usage.
2Loss of time
If TCAMs are used for fast lookup, then access latency is reduced, but power consumption increases
Solution Approach 1:
The patent replaces the power-intensive TCAM comparison mechanism with a more efficient SRAM-based system enhanced by dedicated hash function hardware. The custom hash circuits perform computations in parallel using SRAM, which consumes significantly less power than TCAM's comparator logic while achieving comparable or superior lookup speeds.
3Productivity
If tree-based data structures are used in SRAM, then lookup rate is improved, but latency for individual lookups increases
Solution Approach 1:
The patent pre-computes hash functions and stores them in dedicated hardware circuits before actual lookups occur. This preliminary preparation allows the system to perform fast parallel hashing during runtime without traversing tree structures, eliminating the latency penalty of sequential tree navigation while maintaining high lookup throughput.
Solution Approach 2:
The patent substitutes the sequential tree traversal mechanism with parallel hash function evaluation using dedicated hardware circuits. Instead of navigating through multiple SRAM levels in sequence as tree-based approaches require, the system computes hash values in parallel across multiple circuits, dramatically reducing individual lookup latency while maintaining high throughput.
4Ease of manufacture
If existing hardware lookup tables are used, then fixed key sizes are supported, but adaptability to variable key sizes is limited
Solution Approach 1:
The patent implements dynamic key size support by using configurable hash function circuits that can process variable-length inputs. The hash function hardware is designed to accept keys of different sizes and adaptively compute appropriate hash values, allowing the system to dynamically adjust to different key length requirements without hardware reconfiguration.
Data Source
AI summary
A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit (which may include a programmable hash table) may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the results. Each hash value may be used to access a location in a lookup table in memory to obtain its contents (e.g., a key and associated data). The circuit may include a selection sub-circuit that selects the data of one of the identified locations as an output of the lookup circuit (e.g., one whose key matches the input key). The circuit may modify obtained data prior to its selection and may output a signal indicating the validity of input keys.