Lookup-Table ADPLL for Fast Stable Frequency Locking
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) require a finite amount of time to achieve phase and frequency lock, which is not ideal for applications requiring rapid synchronization and stability.
Innovation Solution
An all-digital phase-locked loop (ADPLL) utilizing a time-to-digital converter, switched capacitor digitally controlled oscillator (SC-DCO), and a phase-locked loop controller with a lookup table to expedite locking by pre-defining optimal switching configurations for various frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional feedback-based PLL locking is used, then phase and frequency lock stability is achieved, but locking time is extended and synchronization speed is reduced
Solution Approach 1:
The patent pre-calculates and stores optimal DCO control values for various desired frequencies in a lookup table before operation. When frequency switching is needed, the system directly retrieves the pre-computed control value from the lookup table, eliminating the need for time-consuming feedback-based locking procedures. This preliminary preparation of control data enables immediate frequency transitions while maintaining phase and frequency alignment.
2Adaptability or versatility
If feedback-based phase locking is implemented, then frequency stability is maintained, but immediate frequency switching capability is lost
Solution Approach 1:
The system pre-computes and stores the exact DCO control values needed for various target frequencies in advance. When a frequency change is required, the lookup table provides the precise control value immediately, allowing the DCO to switch frequencies instantly while the TDC ensures phase continuity by comparing the new frequency phase with the reference phase.
Solution Approach 2:
The time-to-digital converter acts as an intermediary between the DCO and the control system. It measures the phase difference between the DCO output and reference clock, converting this phase information into digital values that guide the lookup table selection. This intermediary mechanism enables rapid frequency switching while maintaining phase coherence across frequency transitions.
3Reliability
If external reference clock is continuously used for locking, then accurate phase synchronization is achieved, but power consumption increases
Solution Approach 1:
Instead of continuously using the external reference clock for phase locking, the system performs phase measurement and frequency switching periodically or on-demand using the lookup table. The TDC and controller only actively engage when frequency changes are needed or periodic synchronization is required, allowing the DCO to operate autonomously between these events, thereby reducing overall power consumption while maintaining synchronization accuracy when needed.
Data Source
AI summary
According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.