Lookup-Table CRC Logic Circuit for Low-Latency Parallel Generation
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Solution Overview
Problem
Existing CRC generation circuits face challenges in achieving area efficiency and low latency while keeping up with increasing data communication bandwidths, particularly in generating larger bit CRC values.
Innovation Solution
A logic circuit that stores N-bit CRC values for one-hot encoded data frames in a lookup table, performs logical AND operations between data frame bits and CRC values, and uses exclusive-OR operations to generate final CRC values, allowing for parallel pipeline operation and efficient CRC calculation for single and multiple data frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional CRC generation circuits are used, then computational accuracy is maintained, but hardware area consumption increases and latency increases
Solution Approach 1:
The CRC generation process is segmented into parallel pipeline stages: data frame input stage, lookup table indexing stage, AND operation stage, XOR accumulation stage, and output stage. Each stage processes a portion of the computation independently, allowing parallel execution that reduces overall latency while maintaining compact hardware area through staged processing.
Solution Approach 2:
The lookup table is pre-computed and stored in memory during the design phase, containing pre-calculated CRC values for all possible data frame patterns. During operation, the circuit only needs to perform table lookup and simple bitwise operations rather than executing the full polynomial division algorithm, dramatically reducing runtime computational requirements and hardware area.
2Reliability
If larger bit CRC values are generated, then error detection capability improves, but computational power consumption increases
Solution Approach 1:
Instead of implementing the full polynomial division algorithm for each CRC bit calculation, the invention uses a lookup table that stores pre-computed CRC values. The runtime operation copies the appropriate pre-computed value through table lookup and bitwise operations, eliminating the need for complex real-time computation and reducing power consumption while maintaining full error detection capability for the specified CRC size.
3Productivity
If conventional CRC circuits are designed to keep up with increasing bandwidths, then data communication speed is maintained, but hardware complexity increases
Solution Approach 1:
The circuit implements a dynamic parallel pipeline architecture where multiple data frames can be processed simultaneously through different pipeline stages. The pipeline can be configured to handle varying data rates and frame sizes, adapting its operation dynamically to match communication bandwidth requirements without proportionally increasing hardware complexity.
Solution Approach 2:
The lookup table-based CRC generator is designed to be universally applicable to multiple CRC polynomial configurations and data frame sizes. By changing the lookup table contents and control parameters, the same hardware circuit can generate different CRC variants (e.g., CRC-8, CRC-16, CRC-32) without requiring separate dedicated circuits for each configuration, reducing overall hardware complexity.
Data Source
AI summary
CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.