Lookup-Table Data Weighted Average Circuit for Fast DAC Linearity
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Solution Overview
Problem
Existing data conversion systems, such as sigma-delta modulators and digital-to-analog converters, face challenges in achieving high linearity due to capacitor mismatch, especially when increasing the resolution, which is not practically realizable with large capacitance requirements.
Innovation Solution
A data weighted average circuit utilizing a lookup table to speed up operations by retrieving pre-stored outputs for various orders and bit widths, allowing dynamic element matching of D/A converting cells without affecting operation delays, thereby enhancing linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of quantizers is increased to reduce quantization noise, then the linearity of multibit DAC must be increased, but this requires large capacitance which is not practically realizable
Solution Approach 1:
The patent applies dynamic element matching by dynamically selecting different capacitor combinations based on the input signal. The capacitor array is switched dynamically through a binary-weighted selector, allowing the system to achieve high linearity without requiring all capacitors to be perfectly matched simultaneously. This dynamic selection process resolves the contradiction by using time-varying configurations rather than static high-precision components.
Solution Approach 2:
The system changes the effective capacitance parameters dynamically by selecting different subsets of capacitors based on the digital input code. Instead of using a fixed large-capacitance configuration for high linearity, the patent varies the active capacitor combinations, allowing the same physical capacitors to serve multiple precision requirements at different times. This parameter variation resolves the capacitance-linearity tradeoff.
2Reliability
If dynamic element matching is implemented to move distortion out of signal band, then circuit operation speed may be affected, but operation delays are affected by various orders and bit-widths
Solution Approach 1:
The patent pre-calculates and stores the optimal capacitor selection patterns in a lookup table during the design phase. During operation, the system simply retrieves pre-computed results from the lookup table based on the input code, avoiding complex real-time calculations. This preliminary action resolves the contradiction by shifting computational burden from runtime to design time, maintaining high speed while achieving dynamic element matching.
Solution Approach 2:
The system uses a lookup table that stores pre-computed mapping relationships between input codes and optimal capacitor selections. Instead of performing complex dynamic selection calculations for each input, the system copies the appropriate pre-stored configuration from the lookup table. This copying approach maintains operation speed independent of circuit order and bit-width, resolving the speed-reliability contradiction.
3Measurement precision
If the number of bits of quantizer is increased to directly reduce quantization noise, then the hardware configuration becomes more complex, but the invention maintains same hardware for various bit widths
Solution Approach 1:
The patent designs a universal capacitor array and control logic that can handle multiple bit-widths and SDM orders using the same hardware configuration. The binary-weighted selector and lookup table approach allows the same physical circuit to support different resolutions by simply changing the lookup table contents, not the hardware structure. This universality resolves the contradiction by achieving high precision without proportionally increasing hardware complexity.
Solution Approach 2:
The system achieves different bit-widths and resolution levels by changing the lookup table parameters rather than modifying the hardware configuration. The same capacitor array and control logic can be reconfigured for different applications by updating the pre-stored mapping data. This parameter-based reconfiguration resolves the contradiction between precision and hardware complexity by decoupling performance from physical structure.
Data Source
AI summary
A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.