Look-up Table Neural Network Inference Hardware
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Solution Overview
Problem
Current neural network implementations require significant computational resources and latency due to the need for multiplications and support for floating-point numbers, which complicates hardware deployment and increases power consumption.
Innovation Solution
The use of look-up tables to perform multiplications and apply activation functions in neural networks, stored in on-chip memory of specialized hardware like FPGAs or ASICs, eliminates the need for multiplication circuitry and floating-point support, allowing for reduced complexity, surface area, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional neural network implementations using software multipliers and floating-point support are used, then computational accuracy is maintained, but computational resources and latency increase significantly
Solution Approach 1:
The patent replaces conventional software-based multiplication operations and floating-point arithmetic with hardware-based lookup tables stored in on-chip memory. This substitution eliminates the need for complex multiplication circuitry and floating-point support, dramatically reducing computational resources and latency while maintaining inference accuracy through pre-computed weight-product values.
2Ease of operation
If hardware multipliers and floating-point support are implemented, then multiplication operations can be performed, but device complexity and surface area increase
Solution Approach 1:
The patent extracts the multiplication operation from the computational process and replaces it with direct lookup table access. By removing the need for multiplication circuitry and floating-point support from the hardware architecture, the design achieves simpler logic, reduced surface area, and lower power consumption while maintaining the essential capability of performing weighted computations.
3Measurement precision
If multiplication circuitry and floating-point support are included, then neural network computations can be performed accurately, but power consumption increases
Solution Approach 1:
The patent substitutes energy-intensive multiplication circuitry and floating-point arithmetic units with low-power lookup table memory structures. By pre-computing and storing weight-product values in on-chip memory, the system eliminates the need for real-time multiplication operations, dramatically reducing dynamic power consumption while maintaining computational precision through direct retrieval of pre-computed values.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing a network input using a neural network to generate a network output for the network input. One of the methods includes maintaining, for each of the plurality of neural network layers, a respective look-up table that maps each possible combination of a quantized input index and a quantized weight index to a multiplication result; and generating a network output from a network input, comprising, for each of the neural network layers: receiving data specifying a quantized input to the neural network layer, the quantized input comprising a plurality of quantized input values; and generating a layer output for the neural network layer from the quantized input to the neural network layer using the respective look-up table for the neural network layer.