Lookup Table Vector Instruction for Parallel Condition Checking

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Solution Overview

Problem

Existing vector processing techniques require numerous scalar instructions to determine whether data in vector elements meet specified conditions, leading to inefficiencies and high demand on vector mask registers.

Innovation Solution

Implementing a lookup table vector instruction (LUT vector instruction) that uses a reference vector to check specified conditions in parallel, reducing the need for scalar checks and minimizing reliance on vector mask registers by using reference values to control vector operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If numerous scalar instructions are used to check conditions for vector elements, then condition checking can be performed, but processing efficiency decreases and vector mask register demand increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidnumber of scalar instructions
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges condition checking functionality into the vector processing architecture itself by introducing a lookup table mechanism that operates in parallel with vector operations. Instead of using separate scalar instructions to check conditions, the system combines condition evaluation with the vector data flow, allowing both operations to occur simultaneously across multiple vector elements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements preliminary action by pre-computing and storing condition results in lookup tables before the actual vector processing occurs. The lookup tables are populated with pre-evaluated condition information, allowing the vector processing to simply retrieve and apply the pre-determined conditions without performing complex scalar comparisons during execution.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If vector mask registers are used extensively to control vector operations, then operation control is achieved, but register demand and resource consumption increase

Engineering Contradiction:
Improvevector operation controlVSAvoidvector mask register demand
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent extracts the condition checking and control functionality from the traditional vector mask register system and relocates it to a lookup table mechanism. This extraction reduces the burden on vector mask registers by providing an alternative path for condition evaluation that does not require extensive register resources, while still achieving the same control objectives.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The lookup table serves as an intermediary between the condition evaluation and vector operation control stages. Instead of directly using vector mask registers to control operations, the system introduces a lookup table as an intermediate structure that stores pre-evaluated condition information, thereby reducing the direct demand on vector mask registers while maintaining control capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12436763B2Lookup table (LUT) vector instruction
Publication Date: 2025.10.07 ADVANCED MICRO DEVICES INC
  • US12436763B2 patent drawing
  • US12436763B2 patent drawing
  • US12436763B2 patent drawing

AI summary

An electronic device includes processing circuitry that executes a lookup table (LUT) vector instruction. Executing the lookup table vector instruction causes the processing circuitry to acquire a set of reference values by using each input value from an input vector as an index to acquire a reference value from a reference vector. The processing circuitry then provides the set of reference values for one or more subsequent operations. The processing circuitry can also use the set of reference values for controlling vector elements from among a set of vector elements for which a vector operation is performed.