Loop Accelerator Context Memory Configuration Bit Distribution
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Solution Overview
Problem
Conventional data processing systems face complexity and increased cost due to lengthy wire connections between configuration memory and processing elements, leading to decreased speed and difficulty in modifying the structure.
Innovation Solution
A loop accelerator with context memories arrayed in row or column directions to transmit configuration bits directly to processing elements, reducing the need for long wires and allowing for a simpler, more easily modifiable structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration memory is connected to PEs by long wires to transmit configuration bits, then all PEs can receive configuration bits, but the wire length increases causing increased cost, complicated design, and decreased transmission speed
Solution Approach 1:
The patent divides the configuration bit transmission into two segments: first from configuration memory to context memories (short distance), then from context memories to PEs (short distance). This segmentation eliminates the need for long wires directly connecting configuration memory to all PEs, reducing wire length and complexity while maintaining reliable configuration bit delivery to all processing elements.
2Reliability
If long wires are used to connect configuration memory to distant PEs, then configuration bits can reach all PEs, but the clock cycle must be set based on the longest wire length, decreasing processing speed
Solution Approach 1:
By segmenting the transmission path through context memories positioned near the PEs, the patent ensures that no single wire needs to span the entire array. The maximum wire length is reduced to the distance from context memory to the farthest PE in its vicinity, allowing for a shorter clock cycle and faster processing while still delivering configuration bits to all PEs.
Solution Approach 2:
Context memories act as intermediary nodes between the configuration memory and the PEs. These intermediaries receive configuration bits from the configuration memory and locally distribute them to nearby PEs, eliminating the need for long direct connections and enabling faster clock cycles.
3Productivity
If a tree-form configuration is used with multiple configuration managers and switches, then configuration bits can be transmitted efficiently, but the structure becomes hierarchical and complicated, reducing ease of modification
Solution Approach 1:
The patent segments the configuration distribution function by placing context memories at strategic locations within the PE array. Each context memory independently manages configuration bits for its local PE group, creating a modular structure that can be easily modified by adding or removing context memories and their associated PEs without redesigning the entire hierarchical tree structure.
Solution Approach 2:
Instead of using a hierarchical tree structure that requires multiple levels of management (SCM, CMs, SMs), the patent transitions to a distributed two-dimensional array structure where context memories are positioned within the PE array grid. This dimensional change simplifies the connection topology and enables easier structural modification through simple array expansion or contraction.
4Device complexity
If context memories are installed in row or column directions of PEs, then configuration bits can be transmitted along the array direction with minimal wires, but additional context memory components are added
Solution Approach 1:
The context memories serve multiple functions: they store configuration bits, act as local distribution points for PEs, and reduce the wiring complexity of the overall system. By consolidating these functions into the context memory components, the patent reduces the total system complexity even though additional memory components are introduced, as they replace the need for extensive wire interconnections.
Data Source
AI summary
Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.