Loop-Aware High-Level Synthesis for Integrated Circuit Throughput
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Solution Overview
Problem
Current high-level synthesis (HLS) tools for integrated circuits (ICs) face challenges in optimizing loop pipelining due to conflicting loop initiation intervals, leading to lower overall data throughput by assuming higher intervals are executed in every loop iteration.
Innovation Solution
The method involves generating an intermediate representation of a design, performing execution information analysis, embedding analysis results, merging regions, and scheduling to determine accurate execution phase and interval information, allowing for optimized loop pipelining that avoids assumptions of higher interval execution, thereby improving data throughput and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current HLS tools assume higher loop initiation intervals are executed in every loop iteration to handle conflicting II requirements, then resource contention is managed, but overall data throughput decreases
Solution Approach 1:
The patent performs execution information analysis beforehand to determine the actual execution phase and interval of each function call. This preliminary analysis allows the scheduler to make informed decisions about resource allocation and loop pipelining, avoiding the conservative assumption that all functions execute every iteration. By knowing in advance which functions are actually called and their execution patterns, the system can optimize both resource management and throughput simultaneously.
2Manufacturing precision
If HLS tools use conservative scheduling assumptions to handle conflicting loop initiation intervals, then design constraints are satisfied, but loop pipelining optimization is reduced
Solution Approach 1:
The patent introduces a feedback mechanism where execution information analysis results are fed back into the scheduling process. The analysis determines actual execution phases and intervals, which then inform the scheduler's decisions. This feedback loop enables the system to satisfy design constraints while simultaneously optimizing loop pipelining, as the scheduler uses accurate execution information rather than conservative assumptions.
3Ease of manufacture
If HLS tools assume higher loop initiation intervals execute every iteration, then resource allocation is simplified, but execution accuracy decreases
Solution Approach 1:
The patent performs preliminary execution information analysis to accurately determine which functions are actually called and their execution patterns. This preliminary action provides precise execution information to the resource allocation process, eliminating the need for conservative assumptions while maintaining allocation simplicity. The analysis results guide resource allocation decisions with high accuracy.
Data Source
AI summary
High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging.