Loop Branch Prediction Bypass Circuit for Superscalar Processors
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Solution Overview
Problem
Modern superscalar processors face challenges in accurately predicting the direction of loop branch instructions, especially in multi-loop nesting scenarios, leading to low prediction precision and speed.
Innovation Solution
A bypass feedback circuit is added to the loop branch prediction algorithm, registering and bypassing prediction results across pipeline stages to improve prediction accuracy by reusing previous prediction results when subsequent PCs match previously registered values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a loop prediction algorithm is used to predict the direction of loop branch instructions, then the prediction precision for loop instructions is improved, but the prediction speed and precision in multi-loop nesting scenarios deteriorate
Solution Approach 1:
The patent pre-calculates and stores prediction results for loop branch instructions in a bypass buffer before they are needed. When the same PC is encountered again, the pre-stored prediction result is directly retrieved from the bypass buffer, eliminating the need for time-consuming table look-ups and complex algorithmic processing, thus significantly improving prediction speed while maintaining high precision
Solution Approach 2:
The patent creates a bypass buffer that stores copies of prediction results from previous loop iterations. Instead of re-computing predictions, the system copies and reuses these stored results when the same PC is detected, reducing processing time and improving prediction speed without sacrificing accuracy
2Measurement precision
If a loop prediction algorithm is used to predict the direction of loop branch instructions, then the prediction precision for loop instructions is improved, but the device complexity increases
Solution Approach 1:
The patent divides the branch prediction system into two independent segments: the main loop prediction algorithm and the bypass buffer mechanism. The bypass buffer is a separate, simple structure that stores pre-computed results, while the main algorithm remains unchanged. This segmentation allows the system to achieve high precision without significantly increasing overall complexity, as each segment performs a specific function independently
Solution Approach 2:
The bypass buffer acts as an intermediary between the PC input and the prediction output. It intercepts repeated PC values and provides pre-stored prediction results directly, preventing these values from undergoing complex algorithmic processing. This intermediary mechanism simplifies the overall system architecture by filtering out cases that would otherwise require complex computation
3Measurement precision
If table look-up operations are performed for branch prediction, then prediction accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent pre-computes and stores prediction results in the bypass buffer during idle periods or previous pipeline stages. When a PC match is found in the bypass buffer, the system directly retrieves the pre-computed result without performing energy-intensive table look-ups, significantly reducing power consumption while maintaining prediction accuracy
Solution Approach 2:
The patent applies a simplified prediction approach for repeated PC values by using the bypass buffer, performing only partial processing (bypassing the main algorithm entirely for matched cases). This partial action reduces energy consumption for the most common case (repeated loop iterations) while maintaining full accuracy through the stored results
Data Source
AI summary
A method for improving an accuracy of a loop branch prediction algorithm by a bypass circuit, comprising: adding a bypass circuit to a loop branch prediction algorithm; and for three pcs entering a pipeline, enabling pc1 fetched in an if0 stage to enter a hybrid branch predictor, and registering pc1; obtaining branch prediction information in an if1 stage, and making a comparison in an if2 stage to obtain a prediction result, registering the prediction result obtained in the if2 stage, and processing pc2 and pc3 in a same way.