Multi-level loop cut process for 3D memory pitch-doubled metal lines
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Solution Overview
Problem
Current semiconductor technologies face challenges in efficiently forming three-dimensional memory devices with pitch-doubled metal lines and structures, which are essential for increasing memory density, due to limitations in lithographic patterning and etching processes.
Innovation Solution
A multi-level loop cut process is employed, involving the formation of elongated loop-shaped conductive material portions and memory pillar structures, followed by an anisotropic etch process to create moat trenches that enclose the memory arrays, allowing for simultaneous patterning and etching of word lines and bit lines, thereby reducing process complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic patterning and etching processes are used, then existing manufacturing capabilities are maintained, but memory density cannot be increased due to pitch limitations
Solution Approach 1:
The patent divides the metal line formation process into multiple stages: first forming mandrel structures at a relaxed pitch, then using spacer deposition to create additional metal lines adjacent to each mandrel. This segmentation allows the final metal line pitch to be half of the original mandrel pitch, effectively doubling memory density while using existing lithographic capabilities.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation. By depositing conformal spacer layers around mandrel structures and then performing anisotropic etching, the process creates additional metal lines in the lateral dimension without requiring higher lithographic resolution, thus achieving pitch doubling.
2Quantity of substance
If pitch-doubled metal lines are formed using conventional methods, then memory density increases, but process complexity and costs increase
Solution Approach 1:
The patent combines multiple functions into a single integrated process flow: mandrel formation, spacer deposition, and loop cut etching are performed in a unified sequence that simultaneously patterns both word lines and bit lines. This merging reduces the total number of separate lithographic and etching steps compared to conventional approaches, thereby reducing process complexity despite achieving pitch doubling.
Solution Approach 2:
The spacer-based pitch doubling process serves multiple purposes: it defines metal line positions, establishes line spacing, and creates the loop cut patterns for word and bit lines. This multi-functionality eliminates the need for separate patterning steps for each metal line set, reducing overall process complexity.
3Manufacturing precision
If aggressive etching is used to create moat trenches, then memory array enclosure is achieved, but pattern collapse and short circuits occur
Solution Approach 1:
The patent applies different etching conditions to different regions: the moat trench etching uses controlled parameters that are less aggressive than full-array etching, while the loop cut regions use targeted removal. This local quality approach ensures proper enclosure without the excessive aggressiveness that causes pattern collapse and short circuits.
Solution Approach 2:
The patent performs preliminary spacer formation and mandrel creation before the moat trench etching step. These preliminary structures serve as protective elements and guides during the subsequent etching process, preventing pattern collapse by maintaining structural integrity until the enclosure is complete.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density by enabling the formation of pitch-doubled metal lines and structures, improving the efficiency and cost-effectiveness of three-dimensional memory device fabrication while minimizing the risk of pattern collapse and short circuits.
Implementation Method 1
performing an anisotropic etch process that removes parts of the first elongated loop-shaped conductive material portions and parts of the second elongated loop-shaped conductive material portions
Data Source
AI summary
First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-shaped conductive material portions over the two-dimensional array of memory pillar structures. Each of the elongated loop-shaped conductive material potions includes a respective pair of line segments and a respective pair of end segments adjoined to ends of the respective pair of line segments. A moat trench that at least partially laterally encloses the two-dimensional array of memory pillar structures can be formed by performing an anisotropic etch process that removes parts of the first and second elongated loop-shaped conductive material portions, thereby separating each loop-shaped conductive material portion into two disjoined line segments.