Loop Delay Circuit for Phase-Shifted Count Value Generation
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Solution Overview
Problem
Existing frequency delta sigma modulation signal output devices face challenges with increased circuit scale and power consumption when operating at higher frequencies, particularly due to the need for multiple delay elements and frequency delta sigma modulators to suppress idle tones and improve signal-to-noise ratio.
Innovation Solution
A delay circuit and count value generation circuit configuration that reduces circuit scale by using a cyclic number control circuit, loop circuit with feedback, and latch circuit to generate measurement signals with different phases, which are then input to counters to detect inversion edges and generate count values, thereby suppressing quantized noise and improving precision without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay elements and FDSMs are used to suppress idle tones and improve SN ratio, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple FDSMs into a single FDSM structure, merging their functions to suppress idle tones without requiring multiple separate circuits. The single FDSM processes multiple measurement signals simultaneously, achieving the same noise suppression effect as multiple FDSMs would provide, thus reducing circuit scale while maintaining measurement precision
Solution Approach 2:
The single FDSM is designed to handle multiple measurement signals with different phases, making it a multi-functional device. It can process N measurement signals simultaneously to generate N output signals, replacing what would traditionally require N separate FDSMs. This universality reduces device complexity while maintaining the ability to suppress quantized noise and improve SN ratio
2Measurement precision
If operation frequency is raised to improve precision, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent introduces periodic phase shifting of measurement signals fed into the FDSM. By periodically varying the phase of input signals, the system achieves better noise distribution and suppression effects that improve measurement precision. This periodic action allows the system to maintain high precision at lower operating frequencies, thereby reducing power consumption compared to continuously operating at high frequencies
3Measurement precision
If multiple measurement signals with different phases are generated using multiple delay elements, then quantized noise is suppressed, but device complexity increases
Solution Approach 1:
The patent implements dynamic phase shifting within a single delay element structure. Instead of using multiple static delay elements, the system dynamically adjusts the phase of the measurement signal as it circulates through the loop. This dynamic approach generates multiple phase-shifted versions of the measurement signal using a single delay element, suppressing quantized noise while reducing device complexity
Solution Approach 2:
The measurement signal is fed back through the delay element multiple times, with each circulation creating a phase-shifted version of the signal. This feedback mechanism allows a single delay element to generate multiple phase-shifted signals that would traditionally require multiple delay elements, thereby suppressing quantized noise while minimizing circuit scale
Data Source
AI summary
A delay circuit includes: a cyclic number control circuit that generates a third signal based on first and second signals generated based on a trigger signal; a loop circuit in which a plurality of delay elements are electrically connected in series, one output of outputs of the plurality of delay elements is fed back to form a loop, and the third signal is input to the delay element at an initial stage; and a latch circuit that latches output values of the plurality of delay elements as latch signals. The second signal is one output among the outputs of the plurality of delay elements. The loop circuit stops the feedback when a cyclic number of loops reaches a prescribed cyclic number.