Loop Entry Cache for Microcontroller NVM Access
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Solution Overview
Problem
Microcontrollers that fetch instructions directly from non-volatile memory (NVM) face performance degradation due to slower access times compared to volatile memory, leading to increased costs when volatile memory is minimized to reduce size and costs.
Innovation Solution
A memory controller with an address comparator and loop entry cache is used to identify and cache loop entry instructions, reducing wait states by prefetching and caching instructions, thereby improving performance and reducing the need for larger volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If instructions are fetched directly from NVM without volatile memory buffer, then cost and size are reduced, but access speed deteriorates
Solution Approach 1:
The memory controller performs preliminary action by detecting backward jumps (loop entries) before the processor needs the instructions, and prefetches the loop body instructions into the prefetch buffer in advance. This ensures that when the processor executes the loop entry instruction, the next instructions are already available in the prefetch buffer, eliminating wait states without requiring large volatile memory.
Solution Approach 2:
The patent introduces an intermediary mechanism - the prefetch buffer with address comparator - that sits between the NVM and the processor. This intermediary detects loop patterns, prefetches instructions, and supplies them to the processor, thereby mediating between the slow NVM and the fast processor to improve access speed without increasing volatile memory size.
2Speed
If prefetch buffers are used to improve access speed, then instruction fetching performance improves, but device complexity increases
Solution Approach 1:
The memory controller performs self-service by using its own resources (address comparator, prefetch buffer) to detect loop entries and prefetch instructions autonomously without requiring external intervention or complex control logic. The address comparator automatically detects backward jumps by comparing current and previous addresses, and the prefetch buffer automatically stores the loop body instructions, enabling the system to self-optimize performance.
3Quantity of substance
If volatile memory is minimized to reduce cost, then manufacturing cost decreases, but wait states increase
Solution Approach 1:
The patent extracts the critical function of reducing wait states from the volatile memory and relocates it to the NVM-based prefetch mechanism. By extracting the loop entry detection and prefetching functionality from the volatile memory domain and implementing it in the NVM memory controller, the system achieves performance improvement without relying on large volatile memory capacity.
Data Source
AI summary
A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.