Out-of-order Loop Execution via Static Time Counter
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Solution Overview
Problem
Current out-of-order superscalar microprocessors face challenges in efficiently executing loops due to excessive power consumption, complex design, and difficulty in tracking data dependencies, leading to performance degradation from dynamic scheduling.
Innovation Solution
A processor with a time counter that statically schedules instructions based on preset execution times, eliminating the need for dynamic scheduling and reducing resource arbitration, allowing for efficient out-of-order execution with lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic scheduling is used for out-of-order execution, then instruction throughput is improved, but power consumption increases excessively
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing dispatch times for instructions during compilation. The time counter unit uses these pre-computed timestamps to schedule instruction dispatch without real-time dynamic scheduling, eliminating the need for complex runtime arbitration logic that consumes power while maintaining out-of-order execution capability.
Solution Approach 2:
The patent replaces the mechanical dynamic scheduling system (comparators, arbitration logic, and control units that continuously monitor and decide instruction dispatch) with a time-based scheduling mechanism. Instructions are dispatched based on pre-assigned timestamps from the time counter, substituting complex mechanical arbitration with simpler time-comparison logic.
2Adaptability or versatility
If dynamic scheduling with reservation stations is used, then out-of-order execution capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex dynamic scheduling infrastructure including reservation stations, central windows, and large-scale arbitration logic. Instead, it implements a streamlined time-counter based dispatch mechanism that maintains out-of-order execution capability without requiring these complex intermediate structures.
Solution Approach 2:
The patent uses a simplified time stamp copying mechanism where pre-computed dispatch times are stored and replicated for instruction scheduling, replacing the need for complex real-time dependency tracking and arbitration copies that exist in traditional dynamic scheduling architectures.
3Productivity
If loop instructions are executed with traditional dynamic scheduling, then processing capability is improved, but performance degrades due to data cache misses
Solution Approach 1:
The patent applies preliminary action by pre-calculating dispatch times for loop instructions during compilation, allowing the time counter to advance and trigger subsequent loop iterations without stalling. This pre-scheduling approach enables the processor to continue fetching and dispatching loop instructions even when data dependencies or cache misses are present, overlapping memory operations with computation.
Data Source
AI summary
A processor includes a loop detection unit to detect an OOO-loop based on the reserved resources for execution of the OOO loop. The processor executes the OOO loop by reading source operand data on first iteration of the loop and write back data on the last iteration of the loop while allowing instructions after the loop to be concurrently executed.