Loop Filter Amplitude Control for Stable Frequency Offset Estimation

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Solution Overview

Problem

In optical digital coherent receiving systems, increased noise in loop filters can lead to reduced amplitude of the phase rotation amount vector, causing accuracy loss and 'flapping' in output characteristics, which degrades bit error rate performance.

Innovation Solution

A loop filter with an amplitude adjustment control unit that maintains the amplitude of the phase rotation amount vector within a predetermined range, using a bit shift circuit and adder to implement multiplier coefficients that adjust based on absolute value judgments of I and Q signals, and a coefficient α switch control unit to optimize filtering speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If noise is increased in the loop filter input signal, then the amplitude of the phase rotation amount vector is reduced, but this causes accuracy loss and flapping in output characteristics

Engineering Contradiction:
Improvefrequency offset estimation accuracyVSAvoidnoise in loop filter input signal
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where the amplitude of the phase rotation amount vector is continuously monitored and fed back to the loop filter. When the amplitude falls below a predetermined threshold, the feedback signal adjusts the loop filter's operation to increase the amplitude back to an appropriate level, thereby preventing accuracy loss and flapping caused by noise-induced amplitude reduction

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the parameter of the phase rotation amount vector amplitude by applying gain adjustment based on the monitored amplitude level. When noise causes the amplitude to drop below the threshold, the system modifies the amplitude parameter through controlled gain application, ensuring the vector maintains sufficient magnitude for accurate frequency offset estimation without exhibiting flapping behavior

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the bit rate per wavelength is increased, then communication capacity is improved, but signal quality is degraded due to reduced OSNR and waveform distortion

Engineering Contradiction:
Improvecommunication capacityVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent replaces traditional analog signal processing with digital signal processing in the coherent receiving system. By using digital loop filters and digital phase rotation amount calculation, the system can maintain signal quality at high bit rates through precise digital processing that compensates for OSNR reduction and waveform distortion effects that become more severe at higher communication capacities

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent employs a composite approach combining coherent detection with digital signal processing techniques. The system integrates multiple processing stages including analog-to-digital conversion, digital loop filtering, and digital phase rotation, creating a composite signal processing chain that maintains reliability while achieving high communication capacity through the synergistic combination of different processing methods

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS8861980B2Loop filter
Publication Date: 2014.10.14 1FINITY INC
  • US8861980B2 patent drawing
  • US8861980B2 patent drawing
  • US8861980B2 patent drawing

AI summary

A loop filter include: a register that stores a result of arithmetic operation performed on a complex signal and outputs the stored complex signal; a first multiplier that multiplies the complex signal output from the register and a predetermined coefficient; an absolute value judging unit that outputs a multiplier coefficient used to control such that the amplitude of the complex signal output from the register is held in a predetermined range; a multiplier that multiplies an output from the first multiplier and the multiplier coefficient; a second multiplier that multiplies an input signal and a value (1−the predetermined coefficient); and an adder that adds an output from the multiplier to an output from the second multiplier and inputs a result of addition into the register.