Loop Filter Combining Multiple TEDs for Stable Timing Recovery
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Solution Overview
Problem
Existing timing recovery loops in digital communication systems face instability due to the complementary yet conflicting advantages and disadvantages of ADC-TED and Slicer-TED, leading to poor reception performance and interference from adaptive equalizer updates.
Innovation Solution
A loop filter and timing recovery apparatus that incorporates multiple timing error detectors, allowing for independent gain parameter configuration, integrating and combining the strengths of multiple timing error messages to stabilize the sampling phase and reduce phase jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ADC-TED or Slicer-TED is used for timing recovery, then timing recovery can be performed, but reception performance becomes unstable due to complementary yet conflicting advantages and disadvantages
Solution Approach 1:
The patent combines multiple timing error detectors (both ADC-TED and Slicer-TED) into a unified timing recovery loop, merging their complementary advantages while mitigating their individual disadvantages through coordinated operation under unified control signals
2Measurement precision
If adaptive equalizer updates are performed during timing recovery, then equalization accuracy improves, but timing recovery stability deteriorates due to interference from coefficient updates
Solution Approach 1:
The patent implements periodic timing recovery operations that are synchronized with and separated from adaptive equalizer update cycles, creating periodic intervals where timing recovery can occur without interference from equalizer coefficient changes
Solution Approach 2:
The patent performs timing recovery operations at predetermined intervals and timing points before or between adaptive equalizer updates, ensuring timing accuracy is maintained independently of equalizer coefficient variations
Data Source
AI summary
A loop filter, and a timing recovery method and apparatus are provided. The loop filter includes: N input terminals configured to receive N first signals; where N is any integer greater than or equal to 2; a source filter, including: an integral signal terminal and an addition terminal; a first gain processing module configured to perform first gain processing on the N first signals to obtain a second signal, and output the second signal to the addition terminal; a second gain processing module configured to perform second gain processing on the N first signals to obtain a third signal, and output the third signal to the integral signal terminal; and a source filter configured to integrate the third signal received by the integral signal terminal to obtain a fourth signal, and obtain a fifth signal according to the fourth signal and the second signal received by the addition terminal.