Loop Filter Reset Scheme for Fast Class D Amplifier Saturation Recovery
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Solution Overview
Problem
Class D amplifiers experience prolonged saturation and output signal distortion due to overloading, with existing solutions failing to achieve less than 1% total harmonic distortion (THD) at full power delivery, particularly at high frequencies.
Innovation Solution
An nth-order loop filter with a hybrid sample-and-hold based saturation recovery scheme, where specific RC integrators are hard reset while others are maintained in a hold state or undergo controlled resets, ensuring selective and controlled discharge of capacitors to prevent oscillations and maintain signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a hard reset is applied to all integrators downstream from a comparator to discharge integrating capacitors during overload recovery, then saturation recovery speed is improved, but output signal distortion exceeds the 1% THD threshold
Solution Approach 1:
The patent applies different reset strategies to different integrators based on their specific roles and characteristics. The first integrator uses a soft reset mechanism that gradually discharges the capacitor through a resistor, while subsequent integrators use hard reset mechanisms. This localized differentiation allows each integrator to recover according to its specific requirements, achieving both fast recovery and low distortion.
Solution Approach 2:
The reset mechanisms are dynamically controlled based on the overload detection state. During normal operation, the integrators function normally without reset intervention. When overload is detected, the reset mechanisms are activated with different timing and characteristics - the first integrator's soft reset begins immediately, while subsequent integrators are reset after a controlled delay, creating a dynamic recovery sequence that optimizes both speed and signal quality.
2Reliability
If current sources are used to inject recovery current into integrating capacitors to damp oscillations, then oscillation damping is improved, but the approach is not robust across all process and temperature corners
Solution Approach 1:
The patent segments the loop filter into multiple integrators, each with its own reset mechanism. This segmentation allows independent optimization of each integrator's recovery behavior. The first integrator handles the primary recovery function with a soft reset, while subsequent integrators provide additional stabilization with hard resets, creating a modular approach that is more robust to variations in process and temperature.
Solution Approach 2:
The system uses feedback from the comparator to detect overload conditions and trigger the appropriate reset sequences. The feedback mechanism monitors the state of the integrators and activates the reset mechanisms only when needed, ensuring that the recovery process adapts to actual operating conditions rather than relying on fixed current injection that may not work across all corners.
3Device complexity
If all integrating capacitors are assumed to be charged in the same direction during recovery current injection, then the control logic is simplified, but the approach fails when this assumption does not hold
Solution Approach 1:
The patent prepares multiple reset mechanisms in advance, each designed for specific integrators. The first integrator is prepared with a soft reset mechanism that can handle any charge state, and subsequent integrators are prepared with hard reset mechanisms. This preliminary preparation ensures that regardless of the charge direction or state of any integrator, the appropriate reset mechanism is already in place and can be activated immediately when overload is detected.
Data Source
AI summary
Examples of amplifiers and nth-order loop filters thereof are configured to enable fast and robust recovery from saturation, while limiting signal distortion at or near full power delivery across multiple process and temperature corners. An example nth-order loop filter comprises n series-coupled resistor-capacitor (RC) integrators. In an example, each of the second RC integrator to the (n−1)th RC integrator has a reset mechanism responsive to a reset signal output from a reset controller when an input signal overload condition is detected at the input. Upon detecting the overload condition, each of the third RC integrator to the (n−1)th RC integrator is hard reset, the nth RC integrator is not reset, and a controlled reset is performed on the second RC integrator to recover from saturation caused by the signal overload condition, while maintaining the output signal below the 1% total harmonic distortion (THD) level at or near full power delivery.