Loop-Latch Multi-Phase Clock Circuit for Low-Delay Timing
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Solution Overview
Problem
Conventional multi-phase non-overlapping clock generation circuits require high-power-consuming D flip-flops, leading to increased noise and delay in output signals due to the need for multiple logic gates and flip-flops, which limits their use in high-frequency signal processing.
Innovation Solution
A multi-phase clock generation circuit utilizing a loop structure of logic gates and latches, eliminating the need for D flip-flops, reduces power consumption, noise, and delay by performing logical operations and latching through NOR or NAND gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If D flip-flops are used to generate multi-phase non-overlapping clock signals, then the clock signals can be generated with correct timing, but the power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the D flip-flop component from the clock generation circuit, replacing it with a latch-based structure. This extraction eliminates the high power consumption associated with D flip-flops while maintaining the essential function of generating multi-phase non-overlapping clock signals through a different architectural approach
Solution Approach 2:
The patent changes the operational parameters of the clock generation circuit by using latches instead of D flip-flops, and by implementing a specific feedback mechanism that controls the timing and phase of clock signals. This parameter change reduces power consumption while preserving timing accuracy
2Adaptability or versatility
If multiple D flip-flops and AND gates are used to generate multi-phase clock signals, then the required phase distribution is achieved, but the noise increases
Solution Approach 1:
The patent removes the AND gates from the circuit structure, replacing the conventional D flip-flop and AND gate combination with a latch-based feedback structure. This extraction reduces the number of logic components, thereby reducing noise while maintaining the ability to generate multiple phases
Solution Approach 2:
The patent merges the functions of phase generation and phase distribution into a unified latch-based feedback structure. By combining these functions, the circuit achieves the required phase distribution capability with fewer discrete components, reducing overall noise
3Adaptability or versatility
If multiple D flip-flops and logic gates are cascaded to generate multi-phase clocks, then the phase separation is achieved, but the delay increases
Solution Approach 1:
The patent extracts and removes the cascaded D flip-flop and AND gate structure that causes cumulative delay. By replacing this with a direct latch-based feedback structure, the circuit achieves phase separation with minimal signal propagation delay
Solution Approach 2:
The patent implements preliminary action by using latches that are pre-configured to capture and hold clock phases at specific timing points. This preliminary latching action ensures that phase separation is achieved without requiring multiple cascaded stages, thereby reducing delay
Data Source
AI summary
A multi-phase clock generation circuit is configured to generate a multi-phase non-overlapping clock signal and includes a loop structure, where input ends and output ends of a plurality of logic gates are electrically coupled head to tail to form the loop structure; and a plurality of latches configured to latch signals at the input ends of the logic gates. The multi-phase clock generation circuit performs a logical operation based on selection signals and clock signals that are received at the logic gates, latches data of upper-stage logic gates that is received at logic gates in a loop through the latches, and outputs multi-phase non-overlapping clock signals through the output ends of the logic gates.