Loop Nest Tiling with Dependency Analysis
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Solution Overview
Problem
Existing tiling approaches in high-performance compilers only consider one loop nest at a time, leading to inefficient memory usage and bus bandwidth requirements when scaling to multiple processors, as they do not effectively manage dependencies between loop nests.
Innovation Solution
A compiler detects series of loop nests, tiles them together, and performs dependency analysis to determine which results from earlier tiles need to be pre-computed, allowing for lazy computation and reducing memory access by keeping data in the cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing tiling approaches process one loop nest at a time, then the implementation is simple, but memory traffic increases and cache efficiency decreases when scaling to multiple processors
Solution Approach 1:
The patent merges multiple loop nests into a unified tiling framework that processes them simultaneously rather than sequentially. The compiler detects series of loop nests and applies tiling across all of them together, creating a coordinated execution plan that reduces memory traffic by keeping related data in cache across multiple loop nest iterations.
Solution Approach 2:
The patent performs preliminary dependency analysis to determine which results from earlier tiles need to be pre-computed before another tile loop executes. This allows the compiler to optimize the execution order and pre-load necessary data into cache, reducing memory traffic during actual execution.
2Device complexity
If existing tiling approaches use standard tiling without dependency analysis, then the compiler is easier to implement, but bus bandwidth requirements increase when scaling to multiple processors
Solution Approach 1:
The compiler performs preliminary dependency analysis to determine which results from earlier tiles need to be pre-computed before another tile loop executes. This analysis is done once during compilation, avoiding runtime overhead while enabling optimized execution that reduces bus bandwidth requirements during parallel processing.
Solution Approach 2:
The dependency analysis mechanism automatically identifies and manages data dependencies between loop nests without requiring manual intervention. The system serves itself by detecting patterns in the code and automatically generating optimized tiling schedules that reduce bus bandwidth requirements.
3Loss of energy
If tile sizes are reduced to improve cache locality, then cache hit ratio increases, but the number of tiles and loop iterations increases
Solution Approach 1:
By merging multiple loop nests into a unified tiling framework, the patent allows larger effective tile sizes to be used while maintaining cache efficiency. The coordinated processing of multiple loop nests means that data loaded into cache for one loop nest can be utilized across several loop nests, effectively increasing the beneficial tile size without proportionally increasing the total number of iterations.
Data Source
AI summary
Described is a technology by which a series of loop nests corresponding to source code are detected by a compiler, with the series of loop nests tiled together, (thereby increasing the ratio of cache hits to misses in a multi-processor environment). The compiler transforms the series of loop nests into a plurality of tile loops within a controller loop, including using dependency analysis to determine which results from a tile loop need to be pre-computed before another tile loop. For dependency analysis, the compiler may use a directed acyclic graph as a high-level intermediate representation, and split the graph into sub-graphs each representing an array. The compiler uses descriptors processed from the graph to determine the controller loop and the tile loops within that controller loop.