Loop Iteration Prediction via Pseudo Branch Instructions
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Solution Overview
Problem
In CISC-type DSPs, the combination of loop support and branch prediction mechanisms interferes with optimal instruction fetching, leading to potential cycle penalties and complex coordination issues.
Innovation Solution
A processor with an instruction fetch unit, an instruction execution unit, a branch prediction unit, and a loop control unit that uses pseudo branch instructions to coordinate loop and branch prediction operations, allowing for sequential instruction fetching and execution without requiring complex coordination between the two mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If both loop support mechanism and branch prediction mechanism are implemented, then processing efficiency is improved, but device complexity increases and coordination becomes complicated
Solution Approach 1:
The patent merges the loop support mechanism and branch prediction mechanism by having the branch prediction unit handle loop branch predictions. The loop control unit provides loop information to the branch prediction unit, which then uses this information to predict loop branch destinations, eliminating the need for separate loop prediction logic and reducing coordination complexity.
Solution Approach 2:
The branch prediction unit is designed to serve multiple functions: it predicts both regular branch instructions and loop branch instructions. By making the branch prediction unit universal, the patent avoids the complexity of having separate prediction mechanisms while maintaining high processing efficiency for both branch and loop constructs.
2Productivity
If loop support mechanism interferes with instruction fetch, then loop execution is optimized, but optimal advanced instruction fetching cannot be achieved when competing with branch prediction mechanism
Solution Approach 1:
The loop control unit provides feedback to the branch prediction unit about loop information (such as loop destination addresses and loop status). This feedback enables the branch prediction unit to make accurate predictions about loop branches, allowing the instruction fetch unit to fetch instructions from the correct location without delay, thus maintaining both loop optimization and advanced fetching capability.
3Productivity
If complex coordination mechanism is implemented between loop support and branch prediction, then optimal instruction fetching is achieved, but device complexity increases
Solution Approach 1:
The patent eliminates complex coordination mechanisms by merging the loop support and branch prediction functions. The branch prediction unit directly uses loop information from the loop control unit to make predictions, creating a unified system that achieves optimal instruction fetching without requiring additional coordination logic.
Data Source
AI summary
This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit branches to the first instruction in the loop and sends a pseudo branch instruction to the instruction execution unit. The instruction execution unit acts as if the last instruction in the block is an instruction for branching to the start address of the block. This is stored in the branch prediction unit and branch prediction is performed thereafter.