Loop Instruction Scheduling Using Relationship Graph Intervals

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Solution Overview

Problem

Existing AI chip code generation is inefficient due to the time-consuming trial-and-error method for determining a target loop interval in loop execution, which adversely affects the efficiency of subsequent code generation.

Innovation Solution

An instruction processing method that constructs a relationship graph of instructions, determines a loop interval based on this graph, gradually reduces the loop interval until successful scheduling is achieved, and adjusts the scheduling time sequence in parallel loop iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the trial-and-error method is used to determine loop interval by testing from lower bound in ascending order, then the loop interval can be determined, but the time consumption is 100 to 1000 times that of a successful scheduling attempt

Engineering Contradiction:
Improveloop interval determination accuracyVSAvoidtime consumption for determining target loop interval
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary analysis of the instruction sequence to construct a relationship graph before loop interval determination. This preliminary action identifies dependency relationships and schedules instructions in advance, allowing the system to start with an initial loop interval calculation based on the relationship graph rather than starting from the lower bound through trial-and-error, thus significantly reducing the time required to determine the target loop interval

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical trial-and-error testing approach with a systematic method based on relationship graph analysis. Instead of mechanically testing loop intervals one by one, the system uses the relationship graph to calculate an initial loop interval and then performs targeted verification, substituting the brute-force mechanical process with a more intelligent analytical approach that reduces time consumption by 100 to 1000 times

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If loop interval determination time is reduced, then code generation efficiency is improved, but the complexity of constructing relationship graph and adjusting scheduling increases

Engineering Contradiction:
Improvecode generation efficiencyVSAvoidcomplexity of instruction processing system
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the instruction sequence into individual instructions and represents them as separate nodes in a relationship graph. This segmentation allows the system to analyze dependency relationships between specific instructions rather than treating the entire loop as a monolithic unit, making the complexity manageable by breaking it down into smaller, analyzable components that can be processed systematically

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The relationship graph serves as an intermediary data structure that mediates between the instruction sequence and the loop interval determination process. This intermediary represents dependency relationships in a visual and computable format, allowing the system to analyze and optimize scheduling without directly manipulating the original instruction sequence, thus managing complexity through an intermediate representation layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250370754A1Instruction processing method and apparatus, device, storage medium, chip, and program product
Publication Date: 2025.12.04 TENCENT TECHNOLOGY (SHENZHEN) CO LTD
  • US20250370754A1 patent drawing
  • US20250370754A1 patent drawing
  • US20250370754A1 patent drawing

AI summary

An instruction processing method and apparatus, a device, a storage medium, a chip, and a program product. The method includes: acquiring an instruction sequence, and constructing a relationship graph of the instruction sequence, the instruction sequence including a plurality of instructions for loop execution; determining a loop interval based on the relationship graph, the loop interval being configured for representing a maximum time interval within which the same instruction is scheduled in two adjacent loop iterations; gradually reducing the loop interval, and determining a previous loop interval as a target loop interval when the plurality of instructions are not capable of being scheduled successfully for the first time within a current loop interval; and adjusting a scheduling time sequence of the plurality of instructions in parallel loop iterations based on the target loop interval, and loading the adjusted instructions onto a chip for running.