Loop Segmentation for Cache Prefetching Optimization
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Solution Overview
Problem
Existing information processing devices face performance degradation due to cache misses, particularly in scenarios where successive memory access occurs, making it difficult to prefetch data effectively in the first portion of loop processing, leading to inefficiencies in cache memory utilization.
Innovation Solution
The approach involves dividing loop processing into first and second loop processing phases, where the first phase accesses and prefetches data using a dedicated sector in the cache memory, and the second phase continues data access and prefetching using a different sector, thereby minimizing cache misses and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If prefetching is performed in loop processing, then data access speed is improved, but cache misses occur in the first portion of loop processing
Solution Approach 1:
The loop processing is divided into two segments: first loop processing for initial data access and prefetching, and second loop processing for continued access. This segmentation allows different cache regions to be utilized at different phases, preventing cache misses in the first portion while maintaining prefetching effectiveness.
Solution Approach 2:
The patent introduces a new dimension of cache memory organization by dividing the cache into multiple regions (first region and second region). This dimensional change allows simultaneous access and prefetching operations to occur in different cache regions, eliminating the conflict that causes cache misses in traditional single-region caches.
2Device complexity
If a single region in cache memory is used for both access and prefetch, then device complexity is reduced, but cache misses increase
Solution Approach 1:
The cache memory is segmented into multiple regions, with the first region dedicated to data access and the second region dedicated to prefetching. This segmentation resolves the conflict between simplicity and performance by adding minimal structural complexity while dramatically improving cache hit rate.
3Productivity
If loop processing is executed without division, then program simplicity is maintained, but performance degrades due to cache misses
Solution Approach 1:
The loop processing is dynamically divided into two phases based on execution timing: the first loop processing handles initial access and prefetching operations, while the second loop processing handles subsequent access. This dynamic division allows the system to adapt to different execution phases, improving performance without requiring complex static restructuring.
Data Source
AI summary
A device includes a processor configured to: divide loop in a program into first loop and second loop when compiling the program, the loop accessing data of an array and prefetching data of the array to be accessed at a repetition after prescribed repetitions at each repetition, the first loop including one or more repetitions from an initial repetition to a repetition immediately before the repetition after the prescribed repetitions, the second loop including one or more repetitions from the repetition after the prescribed repetitions to a last repetition, and generate an intermediate language code configured to access data of the array using a first region in a cache memory and prefetch data of the array using a second region in the cache memory in the first loop, and to access and prefetch data of the array using the second region in the second loop.