Loop-Unrolled DFE Receiver With Duty Cycle Control for ISI Margins
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Solution Overview
Problem
Data communication links face challenges in accurately detecting data signals due to parasitic inductance and capacitance in transmission lines, leading to intersymbol interference (ISI) and difficulties in meeting setup and hold time margin requirements.
Innovation Solution
A data signal receiver circuit with a loop-unrolled phase decision feedback equalizer (DFE) and duty cycle control is employed, which generates logic pulses with widths greater than the unit interval (UI) to compensate for ISI, using a comparator, duty cycle control circuit, and multiplexers to optimize signal sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional DFE designs are used to compensate for ISI, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the DFE operation into distinct phases (sampling phase and hold phase) with different pulse width requirements. The logic low pulse and logic high pulse are generated with different widths tailored to their specific functions, allowing the circuit to meet setup and hold time margins without requiring a uniformly complex wide-pulse generation mechanism throughout the entire circuit.
Solution Approach 2:
The patent dynamically changes the pulse width parameter based on the signal phase and logic level. During the sampling phase, logic low pulses are widened to meet setup margins, while during the hold phase, logic high pulses are widened to maintain signal integrity. This parameter adaptation allows precise ISI compensation without permanently increasing circuit complexity.
2Reliability
If pulse widths are increased to meet setup and hold time margins, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent implements dynamic pulse width control where the pulse duration is adjusted based on the operational phase. The logic low pulse width is dynamically extended during the sampling phase to ensure setup margin compliance, while the logic high pulse width is adjusted during the hold phase. This dynamic adaptation ensures reliability without permanently extending signal transmission time.
Solution Approach 2:
The patent employs periodic phase transitions between sampling and hold phases, with each phase having optimized pulse widths suited to its timing requirements. This periodic structure allows the circuit to achieve reliable data detection through extended pulses during critical phases while maintaining overall timing efficiency through phase alternation.
3Productivity
If loop-unrolled phase DFE with duty cycle control is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the DFE circuit into specialized sub-circuits for different functions: a comparator for signal comparison, a duty cycle control circuit for pulse width adjustment, and multiplexers for signal routing. This segmentation allows each component to be optimized independently, improving overall processing efficiency while managing complexity through functional decomposition.
Solution Approach 2:
The duty cycle control circuit serves multiple functions: it generates both logic low and logic high pulses with appropriate widths, controls timing margins for both setup and hold phases, and adapts to different data patterns. This multi-functionality improves productivity by consolidating multiple control functions into a single circuit block rather than requiring separate circuits for each function.
Data Source
AI summary
A data signal receiver circuit, including: a comparator configured to generate a first data signal based on a comparison of an input data signal and a reference voltage, wherein the first data signal includes a first logic low pulse and a first logic high pulse; and a duty cycle control circuit configured to generate: a second data signal based on the first data signal, wherein the second data signal includes a second logic low pulse responsive to the first logic low pulse, wherein the second logic low pulse has a width greater than a unit interval (UI); and a third data signal based on the first data signal, wherein the third data signal includes a second logic high pulse responsive to the first logic high pulse, wherein the second logic high pulse has a width greater than the UL.