Loop-Unrolled DFE Sampling for 32 Gbps Loop Delay Limits

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional data receivers face timing limitations at high data rates due to the inability to settle feedback tap-weighting logic and analog summer within the required unit intervals, leading to reduced effective time for ISI compensation in DFEs, especially at 32 Gbps.

Innovation Solution

The implementation of loop-unrolled decision feedback equalization using parallel data samplers with tri-state outputs and a regenerative latch portion, which reduces loop delay by removing or replacing multiplexers and latches, allowing tap-weight logic to settle within two unit intervals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional DFE with multiplexers and latches is used, then device complexity is reduced, but loop delay increases causing inability to settle within required unit intervals at high data rates

Engineering Contradiction:

Improvedata rateVSAvoidloop delay

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent divides the DFE structure into parallel segments by unrolling the feedback loop. Instead of a single sequential path with multiplexers, the feedback path is segmented into multiple parallel paths that process different tap weights simultaneously. This segmentation eliminates the need for multiplexers and latches in the critical feedback path, reducing loop delay and enabling settlement within required unit intervals at high data rates like 32 Gbps.

Inventive Principle:

Principle #1Segmentation

2Manufacturing precision

If conventional DFE structure with multiplexers is used, then device complexity is lower, but settling time of tap-weight logic increases

Engineering Contradiction:

Improvesettling timeVSAvoidDFE structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by pre-computing and preparing multiple tap weight values in parallel before they are needed. The loop-unrolled structure calculates all necessary feedback values simultaneously in advance, rather than sequentially computing them one at a time. This preliminary parallel computation ensures that all tap-weight logic settles within the required time window, improving manufacturing precision and signal integrity at high data rates.

Inventive Principle:

Principle #10Preliminary action

3Loss of time

If loop-unrolled DFE is implemented, then settling time of tap-weight logic is reduced, but device complexity increases due to additional data samplers

Engineering Contradiction:

Improvesettling timeVSAvoidnumber of data samplers

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges multiple data sampler functions into a unified loop-unrolled DFE structure. By combining the feedback path with the equalization path in a single integrated structure, the patent eliminates the need for separate multiplexers and latches that would otherwise be required to switch between different feedback values. This merging approach reduces overall device complexity despite the increase in data sampler count, as the integrated structure shares common resources and reduces the total component count.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11323117B1Data sampling with loop-unrolled decision feedback equalization

Publication Date: 2022.05.03 CADENCE DESIGN SYST INC

AI summary

Various embodiments provide for data sampling with loop-unrolled decision feedback equalization. In particular, some embodiments provide for an unrolled first-tap Decision Feedback Equalizer (DFE) loop that comprises parallel data samplers that each include a tri-state output.