Loopback Sampling Circuit for Multi-Clock Link Synchronization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The complexity of digital backend synchronization design and data analysis in two-point synchronous sampling is high, leading to increased area and power consumption, especially in radio-frequency transceiving systems with multiple clock domains.

Innovation Solution

A sampling circuit with a generator, loopback selection module, and loopback sampling module that uses loopback pulse signals for synchronous data transmission, eliminating the need for complex digital backend synchronization, ensuring fixed delay and initial synchronization without additional circuit area or power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional two-point synchronous sampling is used with software sampling enable signals synchronized in clock domains, then sampling synchronization can be achieved, but the digital backend clock synchronization design becomes complex and area/power consumption increases

Engineering Contradiction:
Improvesampling synchronizationVSAvoiddigital backend clock synchronization design
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a loopback pulse signal as an intermediary carrier to transmit timing information between sampling points. Instead of directly synchronizing sampling clocks through complex digital backend design, the loopback pulse signal serves as a mediator that carries timing references across different clock domains, simplifying the synchronization mechanism while maintaining reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the timing synchronization function from the complex digital backend clock synchronization system. By separating the timing reference transmission (via loopback pulse signal) from the data path, the system achieves sampling synchronization without requiring complex digital backend clock synchronization design, thereby reducing area and power consumption

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If traditional two-point synchronous sampling is used, then sampling can be performed, but the analysis process of sampling data becomes complex and time-consuming

Engineering Contradiction:
Improvesampling capabilityVSAvoiddata analysis time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements feedback by transmitting the loopback pulse signal through the same signal path as the data. The received loopback pulse signal provides timing feedback that directly indicates the sampling instant, eliminating the need for complex post-processing analysis. This feedback mechanism allows immediate determination of sampling synchronization status, significantly reducing data analysis time

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If asynchronous clock domains are used for two sampling points, then flexibility is improved, but complete synchronization cannot be ensured and data matching requires complex correlation algorithms

Engineering Contradiction:
Improveclock domain flexibilityVSAvoiddata correlation analysis
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The loopback pulse signal serves as a clock-domain-independent intermediary that carries timing information across asynchronous clock domains. By embedding timing references in the loopback pulse signal rather than relying on direct clock domain synchronization, the system achieves flexibility in clock domain selection while maintaining synchronization accuracy, avoiding complex correlation algorithms

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12506491B2Sampling circuit, method for using sampling circuit, storage medium, and electronic device
Publication Date: 2025.12.23 SANECHIPS TECH CO LTD
  • US12506491B2 patent drawing
  • US12506491B2 patent drawing
  • US12506491B2 patent drawing

AI summary

Provided are a sampling circuit and a sampling method. The circuit comprises: a generator, configured to generate a first loopback pulse signal; a loopback selection module, configured to establish a plurality of loopback links according to a pre-configured connection combination; a link loopback pulse signal transmission module, configured to receive the first loopback pulse signal, and transmit the first loopback pulse signal in the plurality of loopback links; a loopback sampling module, connected to the link loopback pulse signal transmission module and configured to determine, from the plurality of loopback links, a target loopback link on which sampling is to be performed, and sample first link data that is on the target loopback link and passes through a target sampling point, and a sampling storage module, connected to the loopback sampling module and configured to store sampling data in a random access memory.