Loopback Waveguide for Wafer-Level Photonic Integrated Circuit Testing
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Solution Overview
Problem
Wafer level testing of photonic integrated circuits (PICs) requires significant surface area for test structures and off-die test equipment, leading to inefficient use of PIC die space and increased manufacturing costs.
Innovation Solution
A loopback waveguide structure that connects optical transmitting and receiving devices within a photonic integrated circuit, allowing for electrical testing of PICs on a wafer substrate before singulation, using a wafer probing apparatus and an interposer structure with thickness-matched planar dielectric waveguides to minimize alignment requirements and conserve die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer level testing structures are implemented using conventional methods, then testing capability is provided, but significant surface area of the PIC die is consumed
Solution Approach 1:
The patent implements wafer-level testing by transitioning from on-die test structures to off-die test structures formed on the wafer surface in the dimensional space surrounding the PIC dies. Test access layers and test structures are formed in inter-die regions and on wafer surfaces, allowing testing without consuming precious on-die area while maintaining full testing capability
Solution Approach 2:
The patent introduces intermediate structures including test access layers, interconnect layers, and off-die test structures that act as mediators between the PIC devices and test equipment. These intermediate layers provide electrical and optical access to the PICs without requiring direct on-die test structures, thereby conserving die area while enabling comprehensive wafer-level testing
2Area of stationary object
If off-die test structures are used for wafer level testing, then die area is conserved, but alignment precision between test structures and PIC components must be maintained
Solution Approach 1:
The patent employs preliminary alignment actions by forming alignment marks and reference structures during the wafer fabrication process before the actual test structures are created. These pre-formed alignment features enable precise registration of off-die test structures with PIC components during subsequent processing steps, ensuring manufacturing precision without consuming on-die area
Solution Approach 2:
The patent replaces mechanical alignment systems with optical alignment methods using thickness-matched planar dielectric waveguides and optical coupling structures. The waveguides provide inherent alignment tolerance and enable optical coupling between off-die test structures and PIC optical components, reducing the stringency of mechanical alignment requirements while maintaining testing accuracy
3Reliability
If conventional testing methods are used, then testing can be performed, but manufacturing costs increase due to extended process steps
Solution Approach 1:
The patent merges the formation of test structures with the existing wafer fabrication process by integrating test access layers, interconnect layers, and optical waveguide layers into the same processing sequence used for PIC manufacturing. This consolidation eliminates separate test structure fabrication steps, reduces process complexity, and lowers manufacturing costs while maintaining comprehensive testing functionality
Solution Approach 2:
The patent creates multi-functional layers that serve both PIC operational functions and testing functions. The same waveguide layers, interconnect layers, and access structures that enable PIC operation also provide test access pathways, eliminating the need for dedicated test-only structures and reducing overall manufacturing complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective wafer level evaluation of PICs, reducing manufacturing costs and conserving die space by allowing for on-wafer testing of optoelectrical devices and optical interconnects before die separation, while ensuring accurate functionality assessment.
Implementation Method 1
a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry
Data Source
AI summary
A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.