Looped-Back Sampling Clock for High-Speed Slave Data Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face challenges in determining the correct timing to sample received data due to the absence of a clock signal from the slave device, limiting data rate in communication, especially under process, voltage, and temperature variations.
Innovation Solution
A master device employs a sampling circuit that uses a looped-back transmit clock signal via a spare off-chip driver and a delay locked loop to compensate for variations in data timing, allowing accurate sampling without additional terminals or CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the slave device does not provide a clock signal, then the device complexity is reduced, but the sampling timing precision deteriorates due to PVT variations
Solution Approach 1:
The patent implements feedback by loopbacking the transmit clock signal from the first off-chip driver through the second off-chip driver to the sampling circuit. This feedback mechanism allows the master device to use its own transmitted clock signal (after experiencing the same transmission path variations) as the sampling clock, automatically compensating for PVT variations without requiring additional clock signals from the slave device.
Solution Approach 2:
The second off-chip driver acts as an intermediary by receiving the transmit clock signal and supplying it to the sampling circuit's clock input. This intermediary component enables the loopback mechanism, allowing the transmit clock to serve dual purposes: driving the slave device and providing the sampling clock signal.
2Reliability
If tolerances are increased to compensate for timing variations, then the reliability of data sampling is improved, but the data rate decreases
Solution Approach 1:
The patent changes the parameter of sampling timing by dynamically adjusting it based on the actual transmit clock signal that has already accounted for PVT variations. Instead of using fixed tolerances, the system adapts the sampling timing to match the actual clock signal characteristics, enabling both high reliability and high data rate operation.
3Measurement precision
If additional terminals or CPU intervention are used to improve sampling accuracy, then the measurement precision is improved, but the device complexity and ease of operation deteriorate
Solution Approach 1:
The master device serves itself by generating the transmit clock signal, loopbacking it through the off-chip drivers, and using it to clock the sampling circuit. This self-service mechanism eliminates the need for external clock signals from the slave device or CPU intervention, achieving high sampling accuracy while reducing device complexity and improving ease of operation.
Data Source
AI summary
An electronic device including a master device, the master device including an interface component to a slave device. The interface component includes a sampling circuit having a clock input, a transmit clock generator configured to generate a transmit clock, a first off-chip driver configured to receive the transmit clock and provide the transmit clock to the slave device, a second off-chip driver configured to receive the transmit clock and configured to supply the transmit clock to the clock input of the sampling circuit of the interface component and a data input configured to receive data from the slave device. The sampling circuit is configured to sample the received data in accordance with the transmit clock supplied by the second off-chip driver.