Looped Delay Circuit for Accurate Duty Cycle Control

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Solution Overview

Problem

Conventional duty cycle controllers require large area delay circuits to achieve half-period delays, which is physically challenging in chip design and difficult to accurately control at high frequencies due to process variations.

Innovation Solution

A delay circuit comprising a unit delay circuit and a loop counter that adjusts delay time by passing the signal through the unit delay circuit multiple times, allowing for precise control of delay time without the need for a large area, using a loop counter to determine if the desired delay time has elapsed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a large delay circuit with many serially connected inverters is used to delay the clock signal by half period, then the duty ratio control accuracy is improved, but the circuit area increases significantly

Engineering Contradiction:
Improveduty ratio control accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The delay circuit is segmented into multiple smaller delay units (first delay unit, second delay unit, third delay unit, fourth delay unit) instead of using one large delay circuit. Each unit contributes a portion of the total delay, allowing the same half-period delay function to be achieved with reduced area occupation and better layout flexibility.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the operating frequency is increased, then the productivity is improved, but the delay time control accuracy deteriorates due to process variations in large delay circuits

Engineering Contradiction:
Improveoperating frequencyVSAvoiddelay time control accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The delay circuit incorporates controllable delay units with adjustable delay times. The delay controller can dynamically adjust the delay time of each unit based on feedback from the duty detector, allowing the system to maintain accurate delay control across varying operating frequencies and process conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

A feedback mechanism is implemented where the duty detector monitors the duty ratio of the output clock signal and provides feedback to the delay controller. The delay controller adjusts the delay times of the delay units accordingly to maintain the desired duty ratio, compensating for process variations and frequency changes.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If the number of serially connected inverters is increased to achieve half-period delay, then the delay time accuracy is improved, but the device complexity increases

Engineering Contradiction:
Improvedelay time accuracyVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The delay function is divided into multiple independent delay units rather than using a single long chain of inverters. This segmentation reduces the complexity of any individual unit while maintaining the overall delay accuracy through coordinated operation of all units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each delay unit is designed to be a versatile building block that can be replicated and configured in different combinations. The delay controller universally manages all delay units, adjusting their individual delay times to achieve the required half-period delay regardless of process variations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10411675B2Delay circuit and duty cycle controller including the same
Publication Date: 2019.09.10 SK HYNIX INC
  • US10411675B2 patent drawing
  • US10411675B2 patent drawing
  • US10411675B2 patent drawing

AI summary

In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.