Looped Long-Channel FET Structure for Dense Mixed FET Integration
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Solution Overview
Problem
Existing long-channel MOSFET devices face challenges in integrating edge effects due to their length and width dimensions, while short-channel MOSFETs struggle with neglecting these effects, and vertical transport field-effect transistors (VTFETs) have current configurations that are not compatible with lateral FETs in a single chip configuration.
Innovation Solution
A semiconductor structure is designed with a closed-loop arrangement of source, drain, and channel regions, allowing for both long-channel and short-channel FETs to be integrated on the same chip, featuring a gate stack adjoining the channel and using epitaxial growth to form electrically isolated source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long-channel MOSFET devices are used, then edge effects can be neglected and device performance is stable, but integration density and chip area efficiency deteriorate
Solution Approach 1:
The patent transitions from conventional planar FET layouts to a three-dimensional closed-loop configuration where the channel forms a continuous loop structure. This dimensional change allows the channel to efficiently utilize chip area while maintaining long-channel characteristics, resolving the contradiction between device stability and area efficiency.
Solution Approach 2:
The closed-loop channel structure introduces curvature and continuous geometry rather than straight-line configurations. This curved loop design optimizes space utilization on the chip while preserving the long-channel properties needed for stable device performance.
2Productivity
If short-channel MOSFETs are used, then integration density improves, but edge effects cannot be neglected and device performance deteriorates
Solution Approach 1:
By adopting a 3D closed-loop architecture, the invention achieves high integration density through efficient spatial arrangement while maintaining the electrical characteristics of long-channel devices, thus avoiding edge effects despite compact footprint.
3Adaptability or versatility
If vertical transport FETs are integrated with lateral FETs on the same chip, then device versatility improves, but current configuration compatibility and manufacturing complexity worsen
Solution Approach 1:
The closed-loop FET structure serves as a universal platform that can operate in both vertical and lateral transport modes. By configuring the source and drain contacts at different positions on the loop, the same device structure achieves multi-functionality, eliminating the need for separate vertical and lateral FET fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the integration of vertical and lateral FETs on the same chip, maintaining equal gate heights and allowing for primary transport in multiple directions, enhancing the performance and versatility of the transistor structure.
Implementation Method 1
epitaxially growing a first source/drain region on the first fin end surface and a second source/drain region on the second fin end surface
Data Source
AI summary
A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.