Looped Memory Chip Calibration Using a Shared ZQ Resistor
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Solution Overview
Problem
The challenge of efficiently performing ZQ calibration in LPDDR5 packages, where the reduced number of ZQ calibration resistors necessitates sharing among multiple chips due to individual differences, leading to impedance mismatch and signal distortion.
Innovation Solution
A single-loop and double-loop memory device architecture that allows multiple chips to share a common calibration resistor through a master-slave configuration, utilizing ZQ flag signals to sequentially perform calibration operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips share a single ZQ calibration resistor in LPDDR5 packages, then the number of calibration resistors is reduced, but impedance mismatch and signal distortion occur due to individual chip differences
Solution Approach 1:
The patent segments the calibration process into multiple sequential stages, with one stage per chip. Each chip performs calibration individually by sequentially connecting to the shared ZQ resistor through multiplexers, ensuring accurate calibration for each chip despite using a single shared resistor.
Solution Approach 2:
The patent implements preliminary actions by pre-configuring multiplexers and control circuits in each chip to enable sequential access to the shared ZQ resistor. The system prepares calibration pathways in advance, allowing each chip to connect to the resistor when its turn comes in the sequence.
2Productivity
If more chips are placed in one LPDDR5 package to increase capacity, then package capacity increases, but the complexity of managing shared ZQ calibration among more chips increases
Solution Approach 1:
The patent employs dynamic control circuits and multiplexers that can adaptively switch connections based on which chip needs calibration. The system dynamically allocates the shared ZQ resistor to different chips in sequence, enabling flexible management of any number of chips without increasing physical resistor count.
Solution Approach 2:
The patent implements feedback mechanisms where each chip monitors its own calibration status and signals completion to the control system. This feedback enables the sequential calibration process to automatically progress through all chips in the package, managing complexity through automated state tracking.
3Reliability
If sequential calibration is performed for each chip using a shared ZQ resistor, then all chips can be calibrated accurately, but calibration time increases
Solution Approach 1:
The patent implements periodic action by establishing a fixed sequential sequence for chip calibration. Each chip is calibrated in a predetermined order through the shared ZQ resistor, creating a rhythmic, repeating calibration cycle that can be efficiently managed and optimized.
Data Source
AI summary
The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.