LOS Detection Circuit With Positive Feedback for Fast Signal Loss Sensing
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Solution Overview
Problem
Existing LOS detectors in USB and eUSB2 systems have slow response times, leading to potential false detection triggers during normal signal transitions, which is incompatible with the requirement for fast response LOS detection without causing jitter or incorrect system functions.
Innovation Solution
A circuit design that includes differential comparators, positive feedback circuits, and logic circuits to determine the magnitude of differential signal lines, eliminating the need for signal filtering and achieving fast LOS detection within 2 UI, thereby mitigating false triggers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional signal filtering or phase-locked loops are used for LOS detection, then false triggers are reduced, but the response time becomes slow and circuit size increases
Solution Approach 1:
The patent applies positive feedback through cross-coupled inverters to create a latch circuit that maintains the LOS detection state. The feedback mechanism reinforces the detection signal and prevents false triggers by maintaining a stable state once LOS is detected, while the fast switching特性 of the latch circuit enables rapid response within 2 UI
Solution Approach 2:
The patent uses dynamic switching of the latch circuit based on the differential signal state. The circuit transitions between latched and unlatched states dynamically, enabling fast response to LOS events while maintaining stability during normal operation. The dynamic nature of the latch allows it to quickly capture and hold the LOS condition without requiring slow filtering
2Reliability
If traditional signal filtering or phase-locked loops are used for LOS detection, then false triggers are reduced, but circuit size and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the complex filtering and phase-locked loop circuits from the LOS detection system. By removing these bulky components and replacing them with a simple latch circuit composed of cross-coupled inverters, the design achieves false trigger prevention with significantly reduced circuit size and power consumption
Solution Approach 2:
The patent replaces expensive, complex filtering circuits with a simple, inexpensive latch circuit. The latch circuit uses basic logic elements (inverters) that are cheaper and consume less power than traditional filtering or phase-locked loop implementations, while still achieving the required reliability
3Speed
If fast response LOS detection is implemented, then response time is reduced, but false detection triggers increase during normal signal transitions
Solution Approach 1:
The positive feedback in the latch circuit creates a hysteresis effect that prevents false triggers during normal signal transitions. Once the latch is triggered by a genuine LOS event, the feedback maintains the state even if the input signal fluctuates, thereby achieving fast response without increasing false detection rate
Solution Approach 2:
The latch circuit is designed to preemptively prevent false triggers by establishing a stable latched state once LOS is detected. This preliminary action counteracts the tendency of fast-response circuits to generate false detections during normal signal transitions, as the latch maintains its state against subsequent signal variations
Data Source
AI summary
Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.