Lossy Integer Multiplier Synthesis with Analytical Error Correction
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Solution Overview
Problem
Current methods for synthesizing integer multipliers in hardware face challenges in achieving a balance between silicon area and error properties, particularly in determining the effect of truncation in sum of products operations, which is complex and time-consuming, leading to inefficient RTL synthesis.
Innovation Solution
A method for deriving a logic circuit for multiplication as a sum of addends operation with desired rounding precision by determining error requirements, discarding specific columns, and including constants for CCT, VCT, and LMS implementations, thereby systematically creating HDL for faithfully rounded multipliers without simulation or exploration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If truncation is applied to reduce silicon area, then hardware implementation cost is reduced, but error properties deteriorate
Solution Approach 1:
The patent changes the parameters of the multiplier by introducing a correction function f(a,b) that modifies the truncation approach. Instead of simple truncation, the method uses a corrected truncation scheme where the correction function adjusts the least significant bits based on the most significant bits, thereby reducing the error introduced by truncation while maintaining reduced hardware area.
Solution Approach 2:
The correction function f(a,b) acts as an intermediary between the truncated partial products and the final result. This intermediary component processes the most significant bits to generate correction values that are applied to the least significant bits, effectively mediating the trade-off between area reduction and precision maintenance.
2Manufacturing precision
If exhaustive simulation is performed to gather error statistics, then error properties are accurately determined, but time consumption increases
Solution Approach 1:
The patent replaces the mechanical simulation process with an analytical mathematical approach. Instead of performing exhaustive simulations to gather error statistics, the method uses analytic formulae to directly calculate error bounds and statistics, substituting the time-consuming simulation mechanism with a more efficient mathematical computation system.
Solution Approach 2:
The patent performs preliminary analytical derivation of error bounds and statistics before actual multiplier synthesis. By pre-calculating the error characteristics using analytic formulae, the method avoids the need for time-consuming exhaustive simulations during the design process, enabling faster synthesis while maintaining accurate error knowledge.
3Device complexity
If simple truncation schemes are used, then hardware complexity is reduced, but design options and trade-offs become difficult to evaluate
Solution Approach 1:
The patent segments the multiplier into distinct functional components: the truncated partial product array and the correction function. This segmentation allows the design to maintain simplicity in the main multiplication structure while adding a modular correction component that provides flexibility for different error tolerance requirements, thereby preserving design options despite reduced overall complexity.
Data Source
AI summary
A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture.