Low Aspect Ratio Interconnect with Coplanar Liner

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor device manufacturing, existing methods for forming metallic interconnects often result in high aspect ratio interconnects with smaller grain sizes, leading to increased resistivity and poor liner/seed conformity, which affects the performance capabilities of the interconnects.

Innovation Solution

A low aspect ratio interconnect is formed using a metallization layer with a liner that has terminal edges coplanar with the uppermost surface, where the metallic interconnect fills the trench and is polished to match the uppermost surface, reducing grain size and improving resistivity and conformity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If conventional high aspect ratio interconnect structures are used, then the trench can be formed deeper, but the grain size becomes smaller leading to increased resistivity

Engineering Contradiction:
Improvetrench depthVSAvoidresistivity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent changes the aspect ratio parameter of the interconnect trench from high to low by adjusting the trench dimensions. Specifically, the trench is formed with a width and depth relationship that creates a low aspect ratio (width/depth ratio), which fundamentally alters the grain growth characteristics of the metallic interconnect material, resulting in larger grain sizes and reduced resistivity.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If conventional interconnect formation methods are used, then the manufacturing process is simpler, but liner/seed conformity becomes poor

Engineering Contradiction:
Improveprocess simplicityVSAvoidliner/seed conformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by ensuring the liner material is selectively deposited only on the trench sidewalls and bottom, with terminal edges that are coplanar with the uppermost surface of the metallization layer. This localized precision in liner placement ensures excellent conformity with the metallic interconnect material while maintaining overall process simplicity.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If the metallic interconnect is polished to match the uppermost surface, then the surface planarity is improved, but the grain structure may be affected

Engineering Contradiction:
Improvesurface planarityVSAvoidgrain structure
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent applies partial action by performing chemical mechanical polishing (CMP) selectively on the metallic interconnect material to achieve coplanarity with the uppermost surface, while carefully controlling the polishing parameters to remove only the excess material at the surface level. This partial removal achieves the desired surface planarity without excessively affecting the underlying grain structure, preserving the beneficial large grain characteristics.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution results in larger grains with lower resistivity and reduced metallization voids, enhancing the performance and reliability of the interconnects by maintaining the initial post-deposition height and thickness, thus improving the overall device performance.

Implementation Method 1

polishing metallic interconnect material to an upper portion of a liner and an uppermost surface of a metallic interconnect

Methodology Applied
Scientific EffectChemical Mechanical Polishing: Abrasion

Implementation Method 2

etching liner material at the upper portion of the liner and the metallic interconnect material at the uppermost surface of the metallic interconnect to an uppermost surface of a metallization layer

Methodology Applied
Scientific EffectEtching: Ablation

Data Source

PatentUS10672707B2Low aspect ratio interconnect
Publication Date: 2020.06.02 ADEIA SEMICONDUCTOR SOLUTIONS LLC
  • US10672707B2 patent drawing
  • US10672707B2 patent drawing
  • US10672707B2 patent drawing

AI summary

A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.