Low Band Gap Source Drain Alloy for Parasitic Resistance Reduction
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Solution Overview
Problem
As microelectronic devices scale down, the contact resistance of doped source drain structures increases, leading to a larger voltage drop in parasitic source/drain regions, which diminishes device performance and becomes a bottleneck.
Innovation Solution
Forming source/drain regions with a low or zero band gap alloy, such as silicon or germanium alloyed with tin, to reduce parasitic resistance by eliminating the energy barrier at the source/drain contact interface and moving it to the channel interface, where it can be modulated by a gate bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped source drain structures are used in scaled microelectronic devices, then device performance is maintained through conventional doping methods, but contact resistance increases as contact dimension is reduced
Solution Approach 1:
The patent changes the fundamental parameter of the source/drain region from heavily doped semiconductor to low-bandgap alloy material. By alloying silicon or germanium with tin to achieve bandgaps of 0.1 eV or less, the material properties are fundamentally altered to enable low-resistance contacts without relying on heavy doping, thus resolving the contradiction between maintaining device performance and reducing contact resistance in scaled devices
Solution Approach 2:
The patent employs composite alloy materials consisting of silicon-germanium-tin or silicon-tin combinations. These composite materials combine the beneficial properties of each element: silicon provides structural stability, germanium enhances carrier mobility, and tin reduces the bandgap. This composite approach enables simultaneous achievement of low contact resistance and maintained device performance through material composition optimization rather than doping
2Productivity
If channel length is scaled down to improve device performance, then channel resistance reduces, but parasitic source/drain resistance becomes a larger proportion leading to voltage drop
Solution Approach 1:
The patent fundamentally changes the resistivity parameter of the source/drain regions by introducing low-bandgap alloy materials. This parameter change reduces the parasitic resistance to such an extent that even as channel length scales down and the proportion of parasitic regions increases, the absolute voltage drop remains minimal, enabling continued device performance improvement without being bottlenecked by parasitic losses
3Object-affected harmful factors
If heavily doped source drain regions are used to reduce contact resistance, then conduction is improved, but band gap between contacts and regions creates energy barrier
Solution Approach 1:
The patent changes the bandgap parameter from the conventional 1.1 eV (silicon) to 0.1 eV or less through alloying with tin. This dramatic parameter reduction eliminates the energy barrier that normally exists at the metal-contact interface, allowing carriers to pass through without overcoming a significant energy barrier, thus simultaneously reducing contact resistance and eliminating the energy barrier problem
Solution Approach 2:
The low-bandgap alloy material acts as an intermediary between the metal contact and the channel region. By introducing this intermediate layer with a bandgap of 0.1 eV or less, the patent creates a gradual transition that mediates the energy barrier problem, allowing smooth carrier transport from the metal contact through the source/drain region into the channel without encountering a sharp energy barrier
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic resistance, enhances device performance by achieving healthy drive currents and high Ion/Ioff ratios, and allows for dope-less source/drain regions, enabling ambipolar conduction without preferential carrier types.
Implementation Method 1
forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero
Data Source
AI summary
Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.