Low-Bandwidth PLL Demodulation for High-Rate Phase Shift Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed phase demodulation in wireless receivers is limited by the complexity and power consumption of traditional high bandwidth phase-lock loops (PLLs), which are required to maintain lock at high data rates.
Innovation Solution
A low bandwidth phase-lock loop combined with a fast phase change detection circuit, which generates multiple phases and uses a fast path phase change detection scheme to maintain lock without the need for high bandwidth PLLs, allowing for high-speed demodulation at reduced complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high bandwidth phase-lock loop is used for high-speed phase demodulation, then the data rate can be increased, but the complexity and power consumption increase significantly
Solution Approach 1:
The system segments the phase demodulation function into two independent parts: a low bandwidth PLL that maintains phase lock and a fast phase change detection circuit that detects phase transitions. This segmentation allows each component to be optimized independently - the PLL for stability and the detection circuit for speed - avoiding the need for a complex high bandwidth PLL while achieving high-speed demodulation capability.
Solution Approach 2:
The fast phase change detection circuit acts as an intermediary between the low bandwidth PLL and the data output. It monitors the PLL output for phase changes and generates data signals accordingly, enabling high-speed phase demodulation without requiring the PLL itself to operate at high bandwidth, thus reducing overall system complexity.
2Speed
If a high bandwidth phase-lock loop is used for high-speed phase demodulation, then the data rate can be increased, but the power consumption increases
Solution Approach 1:
By segmenting the phase demodulation into a low bandwidth PLL and a fast detection circuit, the power consumption is distributed efficiently. The PLL operates at low bandwidth consuming minimal power, while the fast detection circuit consumes power only during phase transition events, resulting in lower overall power consumption compared to a continuously operating high bandwidth PLL.
Solution Approach 2:
The fast phase change detection circuit automatically detects phase transitions and generates data signals without requiring the PLL to increase its bandwidth or processing speed. This self-service mechanism enables high-speed demodulation capability while the PLL maintains its low-power operation, effectively decoupling data rate from power consumption.
3Device complexity
If a low bandwidth phase-lock loop is used, then the complexity and power consumption are reduced, but the ability to maintain lock at high data rates is compromised
Solution Approach 1:
The fast phase change detection circuit serves as an intermediary that monitors the PLL output for phase changes and generates data signals accordingly. This allows the low bandwidth PLL to maintain stable phase lock while the detection circuit ensures high-speed phase transition detection, preserving both reliability and data rate capability.
Solution Approach 2:
The system uses feedback from the fast phase change detection circuit to the data output stage, ensuring that phase transitions are accurately captured and converted to data signals. This feedback mechanism maintains reliable phase demodulation at high data rates even though the PLL itself operates at low bandwidth.
Data Source
AI summary
Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.