Low-Bandwidth PLL Using Frame Clock and On-Chip Loop Filter
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Solution Overview
Problem
Conventional phase-locked loops in integrated circuits face challenges with low bandwidth operation, particularly in audio applications, due to large capacitors required for low frequency operation, which are impractical for on-chip integration, and instability issues with serial clock signals, leading to complexity and cost increases.
Innovation Solution
A phase-locked loop system utilizing a frame clock signal as the reference, with a loop filter design that includes a sample and reset circuit, feed forward integrator, and feed forward stabilizer, amplifying capacitance to allow on-chip integration of capacitors and reduce component count, thereby achieving a low bandwidth response without the need for a master clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional phase-locked loops use large capacitors for low frequency operation, then low bandwidth operation is achieved, but on-chip integration becomes impractical
Solution Approach 1:
The patent transforms the loop filter from a continuous-time analog filter to a discrete-time digital filter implemented in the sigma-delta modulator. This parameter change allows the system to achieve low bandwidth operation without requiring large physical capacitors, as the digital implementation uses computational operations rather than physical energy storage elements.
Solution Approach 2:
The patent replaces the traditional analog loop filter circuitry (which requires physical capacitors) with a digital signal processing approach using a sigma-delta modulator. This substitution eliminates the need for large on-chip capacitors while maintaining the low bandwidth characteristic through digital filtering operations.
2Productivity
If conventional phase-locked loops use serial clock signals as reference, then clock multiplication is achieved, but instability issues arise
Solution Approach 1:
The patent employs a phase-locked loop with feedback to lock the sigma-delta modulator clock to the frame clock reference. The feedback mechanism continuously adjusts the VCO output to maintain a stable phase relationship, eliminating the instability issues associated with simple clock multiplication while preserving the clock multiplication capability.
3Reliability
If master clock is added to provide stable reference, then signal stability is improved, but system complexity and cost increase
Solution Approach 1:
The patent makes the frame clock serve dual functions: it provides both the data synchronization reference for the serial interface and the phase-locked loop reference for clock generation. This multi-functionality eliminates the need for a separate master clock while maintaining signal stability, thereby reducing system complexity and component count.
Data Source
AI summary
A signal processing system includes a phase-locked loop to provide an output signal used, for example, as a delta sigma modulator operating clock signal. In at least one embodiment, a frame clock that provides synchronization for one or more blocks of data is used by the phase-locked loop as a reference signal. Utilizing the frame clock as the reference signal allows the signal processing system to reduce the number of clock signals present in the signal processing system. In another embodiment, a phase-locked loop includes a loop filter that utilizes a sample and reset circuit, a feed forward integrator, and a feed forward stabilizer to provide a low frequency phase-locked loop bandwidth. In at least one embodiment, the feed forward integrator amplifies capacitance of the sample and reset circuit, which reduces the size of loop filter capacitors and, thus, allows on-chip capacitor integration.