Low-Bit ADC Receiver Architecture for SerDes Power Efficiency
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Solution Overview
Problem
High-speed digital ICs in SerDes systems face significant power efficiency challenges due to the need for high-resolution ADCs, which consume excessive power, especially in short and medium reach applications where higher resolution is not justified, leading to increased power consumption without proportional benefits in signal integrity.
Innovation Solution
A receiver architecture that employs a lower resolution analog-to-digital converter (ADC) without a digital signal processor (DSP), merging analog-to-digital conversion with data recovery and error signal generation, and using continuous time linear equalization and automatic gain control to adapt equalization loops, reducing the number of bits required for ADC operation to 3, thereby minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-resolution ADC (6-bit to 8-bit) is used to handle long reach channels, then signal integrity is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic ADC resolution adjustment where the ADC operates at different resolutions based on channel conditions. For short reach channels with better signal quality, a lower resolution (e.g., 3-bit) ADC is used, reducing power consumption. For long reach channels requiring higher signal integrity, the resolution can be increased. This dynamic adaptation resolves the contradiction by matching ADC resources to actual channel requirements rather than using fixed high-resolution settings universally.
Solution Approach 2:
The patent changes the resolution parameter of the ADC from fixed high-resolution (6-8 bits) to variable resolution including lower settings (3-bit). By adjusting this key parameter based on application requirements, the system achieves power efficiency for short/medium reach applications while maintaining the capability for high signal integrity when needed for long reach channels.
2Use of energy by moving object
If ADC resolution is reduced to 3 bits for power efficiency, then power consumption decreases, but signal equalization capability is compromised
Solution Approach 1:
The patent merges the ADC functionality with data recovery and error signal generation functions that were previously separate. By integrating these functions, the system compensates for the reduced equalization capability of low-resolution ADC through combined processing, maintaining effective signal recovery while using only 3-bit ADC for power efficiency.
Solution Approach 2:
The ADC is designed to perform multiple functions: analog-to-digital conversion, data recovery, and error signal generation. This multi-functionality allows a low-resolution 3-bit ADC to compensate for its limited equalization capability by leveraging additional processing functions, thereby maintaining adequate signal equalization performance while achieving power efficiency.
3Device complexity
If DSP is eliminated to improve power efficiency, then device complexity is reduced, but data recovery and equalization precision may be affected
Solution Approach 1:
The patent combines data recovery and error signal generation functions directly within the ADC circuitry, eliminating the need for a separate DSP block. This integration reduces device complexity and power consumption while maintaining data recovery precision through optimized hardware implementations of these functions within the ADC itself.
Solution Approach 2:
The patent extracts and removes the DSP component from the receiver architecture, taking out the digital signal processing function that was previously a separate block. By eliminating this component and integrating its necessary functions into the ADC, the system reduces complexity while maintaining essential data recovery capabilities.
Data Source
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AI summary
A receiver (100) includes: an automatic gain controller (AGC) (104) configured to receive an analog signal; an analog-to-digital converter (ADC) (106) configured to receive an output from the AGC (104) and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data (111), and a least significant bit of the digitized signal corresponds to an error signal (109); and an adaptation unit (110) configured to control the AGC (104), the ADC (106), or both the AGC (104) and the ADC (106), based at least in part on the digitized signal to achieve a desired data digitization and data slicing.