Low Capacitance Interconnect Structures via Composite Insulator
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Solution Overview
Problem
Conventional through-silicon vias (TSVs) in semiconductor devices face challenges such as reduced circuit density due to space occupation, increased capacitance, and manufacturing yield issues due to thin oxide layers and topographical discontinuities caused by chemical mechanical polishing.
Innovation Solution
The implementation of a composite insulator with a low-K dielectric material and a high-K dielectric material, selectively deposited and etched to form a thick insulator layer, reducing capacitance and preventing erosion, while also alleviating stress and delamination risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional through-silicon vias (TSVs) are used to electrically connect the die to the package substrate, then the package footprint is reduced and electrical performance is improved, but circuit density within the die is reduced due to space occupation
Solution Approach 1:
The patent applies local quality by creating a composite insulator structure with different dielectric materials (low-K and high-K) in different regions of the TSV. The low-K material is positioned where capacitance reduction is most critical, while the high-K material provides mechanical support and stress relief where needed. This localized optimization allows the TSV to maintain small dimensions for high circuit density while achieving low capacitance for improved electrical performance.
2Manufacturing precision
If chemical mechanical polishing is used to planarize the substrate surface, then surface flatness is improved, but topographical discontinuities and thin oxide layers are caused leading to manufacturing yield issues
Solution Approach 1:
The patent applies beforehand cushioning by depositing a thick insulator layer comprising low-K and high-K dielectric materials before the chemical mechanical polishing process. This composite insulator structure acts as a cushion that protects the underlying conductive structures from erosion and damage during polishing, preventing topographical discontinuities and maintaining manufacturing yield while still achieving the required surface flatness.
3Area of stationary object
If a thin oxide layer is used in the TSV structure, then the TSV dimensions are reduced improving circuit density, but capacitance increases and manufacturing yield decreases
Solution Approach 1:
The patent applies composite materials by creating a multi-layer insulator structure with both low-K and high-K dielectric materials. The low-K material (such as fluorinated oxide or carbon-doped oxide) provides low capacitance properties, while the high-K material (such as silicon nitride or silicon oxynitride) provides mechanical strength and stress management. This composite approach enables the TSV to maintain small dimensions for high circuit density while achieving reduced capacitance through the low-K layer.
4Loss of energy
If the insulator layer is made thicker to reduce capacitance, then capacitance is reduced, but the structure becomes more prone to erosion and delamination
Solution Approach 1:
The patent applies composite materials by combining low-K and high-K dielectric materials in a layered insulator structure. The low-K material reduces capacitance, while the high-K material (such as silicon nitride) provides enhanced mechanical strength and adhesion. This composite structure achieves the dual benefit of reduced capacitance through the low-K layer while maintaining structural stability and resistance to erosion through the high-K layer.
Solution Approach 2:
The patent applies parameter changes by carefully controlling the thickness, composition, and physical properties of both low-K and high-K dielectric materials. By optimizing parameters such as the dielectric constant, mechanical stress, and interfacial adhesion energy of each layer, the patent achieves a balance where the insulator structure is thick enough to reduce capacitance but remains structurally stable and resistant to erosion and delamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced capacitance, improved circuit density, and enhanced manufacturing yield by maintaining a stable insulator layer and preventing conductive structure shorting.
Implementation Method 1
a composite insulator with a low-K dielectric material and a high-K dielectric material, selectively deposited and etched to form a thick insulator layer
Data Source
AI summary
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.