Low Capacitance Precision Resistor Segmentation
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Solution Overview
Problem
The challenge in semiconductor devices is forming precision resistors in bulk silicon substrates without incurring a large capacitive penalty, as the vertical scaling of gate stacks and implementation of pre-metalized gates make it difficult to pattern resistors effectively.
Innovation Solution
The method involves forming low capacitance resistor segments in the source/drain region of a substrate by patterning and etching silicon segments, filling the spaces between them with an insulating material, and converting the silicon segments to polycrystalline silicon through dopant implantation and annealing, while maintaining electrical connection through end pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a precision resistor is moved into the diffusion substrate, then the ability to pattern the resistor is improved, but the capacitance increases significantly
Solution Approach 1:
The resistor is divided into multiple segments separated by trenches filled with insulating material. This segmentation isolates different parts of the resistor, reducing the capacitive coupling between adjacent regions while maintaining the overall resistive function. The insulating material in the trenches acts as a capacitor blocker, reducing total capacitance.
Solution Approach 2:
The harmful capacitive coupling is extracted and removed by introducing insulating material into the trenches between resistor segments. This extraction of the harmful effect (capacitance) allows the resistor to maintain low capacitance while still being formed in the substrate where patterning is feasible.
2Productivity
If vertical scaling of gate stacks is implemented, then device integration is improved, but the ability to pattern precision resistors deteriorates
Solution Approach 1:
The resistor structure extends into the vertical dimension by forming segments at different depths or utilizing the thickness of the substrate. This dimensional approach allows resistors to be formed in highly integrated devices with scaled gate stacks, as the resistor pattern can be defined in the lateral plane while the vertical structure provides the resistive path through doped regions.
3Ease of manufacture
If pre-metalized gates and replacement gates are used, then manufacturing efficiency is improved, but precision resistor patterning becomes extremely difficult
Solution Approach 1:
The resistor is segmented into multiple sections separated by insulating trenches, which can be formed using standard fabrication processes compatible with pre-metalized gates and replacement gates. This segmentation allows the resistor to be defined in the substrate using conventional lithography and etching, maintaining manufacturing efficiency while achieving precise resistor characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of low capacitance precision resistors in bulk substrates without capacitive coupling, enabling their integration into semiconductor devices without incurring a capacitive penalty, thus facilitating their use in highly integrated semiconductor devices.
Implementation Method 1
converting the silicon segments to polycrystalline silicon, e.g., by implanting a dopant into the silicon segments to amorphize the silicon
Implementation Method 2
annealing the amorphized silicon
Data Source
AI summary
A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.