Low Capacitance Semiconductor Surge Protection Device
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Solution Overview
Problem
Existing surge protection devices face challenges in achieving low capacitance and low breakover voltage characteristics, particularly for high-speed communication lines, due to the diffusion of impurities during high-temperature processing, which increases capacitance and reduces control over breakover voltage.
Innovation Solution
The formation of small-area, shallow buried regions on a semiconductor substrate with a high dopant concentration, covered by an epitaxial semiconductor layer, maintains localized impurity concentration and minimizes capacitance, allowing for precise control over breakover voltage and increased current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature and long term diffusion process is used to form buried regions deeply in the wafer, then the breakover voltage can be controlled, but the capacitance of the device increases and manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by forming the buried regions with precise dopant concentration and distribution before the subsequent base region formation. The buried regions are pre-configured with specific impurity concentrations (e.g., 10^19 to 10^20 atoms/cm³) and depths (e.g., 1-5 micrometers) to establish the desired breakover voltage characteristics before any diffusion processes occur during base region formation, thereby preventing unwanted dopant spread that would increase capacitance.
Solution Approach 2:
The patent employs parameter changes by precisely controlling dopant concentration, diffusion depth, and thermal processing parameters. The buried regions are formed with specific impurity concentrations (10^19 to 10^20 atoms/cm³) and depths (1-5 micrometers), and the base region is formed with lower impurity concentration (10^16 to 10^18 atoms/cm³). These controlled parameter variations enable precise breakover voltage control while minimizing capacitance by limiting the spatial extent of high-concentration dopant regions.
2Manufacturing precision
If buried regions are formed with high impurity concentration to reduce breakover voltage, then low breakover voltage is achieved, but the capacitance increases due to larger junction area
Solution Approach 1:
The patent applies local quality by creating highly localized buried regions with high impurity concentration (10^19 to 10^20 atoms/cm³) at specific depths (1-5 micrometers) beneath the surface, while the overlying base region maintains lower impurity concentration (10^16 to 10^18 atoms/cm³). This localized high-concentration doping in confined regions enables low breakover voltage through enhanced field emission at these specific locations without significantly increasing the overall junction capacitance, as the high-concentration regions are spatially restricted rather than uniformly distributed.
3Quantity of substance
If long diffusion time (30 hours) is used to achieve deep buried regions, then dopant concentration is sufficient, but manufacturing time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-forming the buried regions with the required dopant concentration and depth using optimized diffusion or implantation processes before base region formation. The buried regions are pre-configured with specific impurity concentrations (10^19 to 10^20 atoms/cm³) and depths (1-5 micrometers) to establish the desired breakover voltage characteristics before any subsequent processing, thereby eliminating the need for extended diffusion times later in the manufacturing process.
Solution Approach 2:
The patent employs parameter changes by optimizing diffusion temperature, time, and dopant source concentration to achieve the required dopant profiles in reduced time. The buried regions are formed with specific impurity concentrations (10^19 to 10^20 atoms/cm³) at controlled depths (1-5 micrometers) using parameters such as diffusion temperature (900-1100°C) and time (1-10 hours), representing a significant reduction from conventional 30-hour processes while maintaining the necessary dopant quantities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in surge protection devices with low capacitance and low breakover voltage, suitable for high-speed communication lines, while maintaining a high degree of control over electrical characteristics and reducing the complexity and cost of fabrication.
Implementation Method 1
high temperature processing steps cause the impurities to diffuse outwardly in all directions in the wafer
Implementation Method 2
The impurity concentration of the buried regions determine the breakover voltage of the thyristor device
Data Source
Figure 1~2
Figure 3~4
Figure 5~7b
AI summary
A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).