Low-Capacitance Through-Substrate Via Structure for Stable Signal Speed
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Solution Overview
Problem
Semiconductor devices with through substrate conductive paths face reliability issues due to parasitic capacitances that affect performance and increase power consumption, and these capacitances may degrade over time.
Innovation Solution
The introduction of additional capacitors in series with the TSV capacitance, coupled to a reference voltage, to maintain the composite capacitance below target levels by isolating individual capacitances, thereby reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through substrate conductive paths are formed, then connectivity between substrate layers is improved, but parasitic capacitance increases causing performance degradation
Solution Approach 1:
The conductive path is segmented into multiple sections by inserting dielectric material in alternating pattern with conductive material along the via structure. This segmentation divides the continuous conductive path into discrete segments separated by low-k dielectric layers, reducing the overall parasitic capacitance while maintaining electrical connectivity between layers.
2Ease of manufacture
If conventional TSV structure is used, then manufacturing simplicity is maintained, but capacitance increases reducing operating speed
Solution Approach 1:
The alternating conductive and dielectric layers are formed preliminarily during the TSV fabrication process before final via completion. By pre-forming the low-k dielectric layers between conductive segments during the manufacturing process, the structure is prepared in advance to minimize capacitance effects, enabling faster signal propagation without complicating the overall manufacturing flow.
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 3A~3E
AI summary
Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.