Low Clock Supply Voltage Interruptible Sequential Logic Design
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Solution Overview
Problem
Modern microprocessors and SoCs face significant power dissipation challenges due to clock grid and sequential load, with limited options for reducing power consumption while maintaining performance and frequency targets, especially given constraints on supply voltage and process technology.
Innovation Solution
Implementing low clock supply voltage interruptible sequential logic designs that operate the clock path at a lower power supply than the data path, using separate power supplies to minimize power consumption and delay overhead, and incorporating local clock inverters shared across multiple flip-flops to prevent DC short circuit currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock path operates at the same supply voltage as the data path, then the sequential logic can operate reliably, but the power consumption is high
Solution Approach 1:
The patent segments the power supply system into two distinct voltage domains: a first power supply voltage for the clock path and a second power supply voltage for the data path. This segmentation allows independent optimization of power consumption and reliability for each path, enabling the clock path to operate at lower voltage while maintaining sequential logic reliability through proper voltage domain separation and level shifting mechanisms.
Solution Approach 2:
The patent applies local quality by providing different power supply voltages to different parts of the circuit: the clock path receives a first voltage while the data path receives a second voltage. This localized voltage assignment optimizes power consumption in the clock distribution network while maintaining adequate voltage levels for reliable data processing in the data path.
2Use of energy by moving object
If separate power supplies are used for clock and data paths, then power consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent employs universal level shifting mechanisms that can handle multiple voltage domains and signal types. The level shifters are designed to work across different voltage combinations, providing a multi-functional interface between the first and second power supply domains, which reduces the need for dedicated circuitry for each voltage transition.
Solution Approach 2:
The patent introduces level shifters as intermediary components between the first and second power supply domains. These intermediaries facilitate safe signal transitions between different voltage levels, isolating the clock and data paths while enabling controlled interaction, thus managing complexity through standardized interface mechanisms.
3Use of energy by moving object
If lower supply voltage is used for clock path, then power savings are achieved, but delay overhead increases
Solution Approach 1:
The patent changes the voltage parameter of the clock path by supplying it at a first power supply voltage that is lower than the second power supply voltage used for the data path. This parameter change reduces dynamic power consumption in the clock distribution network and sequential logic while managing delay through careful voltage level selection and buffer design.
Data Source
AI summary
An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.