Low-Contention Read Bitline Circuits for Ultra-Low-Voltage SRAM
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Solution Overview
Problem
High-performance multi-core microprocessors and digital systems face challenges in reducing power consumption while maintaining performance, particularly due to high contention current and leakage power issues at low supply voltages, which limits the minimum operating supply voltage and increases power consumption in semiconductor devices like register files and SRAMs.
Innovation Solution
Implementing ultra-low-temperature (ULT) and ultra-low-voltage (ULV) designs that utilize low threshold voltage transistors and keeperless flip-flops to reduce contention current, improve read delay, and maintain noise performance, enabling lower supply voltage operation with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional circuits operate at low supply voltages, then power consumption should be reduced, but contention current increases and minimum operating voltage is limited
Solution Approach 1:
The patent changes the operating parameters by implementing ultra-low-temperature (ULT) and ultra-low-voltage (ULV) designs that utilize low threshold voltage transistors. This allows the circuit to operate reliably at supply voltages as low as 0.4V while maintaining acceptable contention current levels, thereby resolving the contradiction between reducing power consumption and maintaining minimum operating voltage requirements
Solution Approach 2:
The patent employs dynamic voltage scaling and adaptive voltage positioning techniques that allow the circuit to dynamically adjust its operating voltage based on workload and performance requirements. This enables the system to operate at ultra-low voltages during light loads while maintaining higher voltages during heavy loads, effectively resolving the contradiction between power reduction and operational reliability
2Loss of energy
If threshold voltage is reduced to enable lower supply voltage operation, then power consumption decreases, but leakage current increases
Solution Approach 1:
The patent utilizes low threshold voltage transistors operating at ultra-low temperatures to change the physical parameters of transistor operation. At ULT conditions, the increased carrier mobility and reduced thermal effects compensate for the higher leakage current inherent in low-VTH devices, allowing the system to achieve lower power consumption without excessive leakage penalties
Solution Approach 2:
The patent applies different threshold voltage characteristics to different parts of the circuit based on functional requirements. Critical path transistors use low-VTH devices for speed, while non-critical transistors use higher-VTH devices to minimize leakage, thereby resolving the contradiction between power consumption and leakage current at the circuit level
3Object-affected harmful factors
If keeper circuits are added to maintain signal levels, then noise performance improves, but contention current increases
Solution Approach 1:
The patent removes traditional keeper circuits from the design and replaces them with alternative mechanisms such as cross-coupled inverters and adaptive voltage positioning that maintain signal levels without the high contention current penalty of conventional keepers, thereby resolving the contradiction between noise performance and contention current
Solution Approach 2:
The patent introduces intermediate voltage levels and adaptive voltage positioning circuits that act as mediators between the signal nodes and ground. These intermediary circuits provide noise immunity by maintaining intermediate voltage levels without creating the direct low-impedance paths to ground that cause high contention current in traditional keeper circuits
Data Source
AI summary
A disclosed example includes a read local bitline; and a plurality of pulldown transistor circuits coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first low threshold voltage transistor, the first low threshold voltage transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor, the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first low threshold voltage transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information.