Low CTE Dielectric Interposer for Thermal Stress Relief
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Solution Overview
Problem
Existing interposers in microelectronic assemblies face challenges in thermal expansion mismatch and bonding interface reliability due to high coefficients of thermal expansion, leading to potential delamination and cracking, and require improved connectivity and spatial matching with microelectronic elements and circuit panels.
Innovation Solution
A method involving the formation of substantially rigid solid metal posts with a dielectric layer of low thermal expansion (less than 8 ppm/°C) and wettable contacts to bond with microelectronic elements and circuit panels, ensuring no lateral interconnects between post end surfaces, and using redistribution layers to achieve spatial alignment and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials with high CTE are used in interposers, then manufacturing is easier and cost is lower, but thermal expansion mismatch causes delamination and cracking at bonding interfaces
Solution Approach 1:
The patent changes the thermal expansion parameter of the dielectric material by selecting materials with CTE less than 8 ppm/°C (such as ceramic substrates like alumina, aluminum nitride, or silicon carbide) to match the CTE of semiconductor chips and PCBs. This parameter change resolves the thermal expansion mismatch problem that causes delamination and cracking at bonding interfaces, thereby improving reliability without significantly complicating the manufacturing process.
Solution Approach 2:
The patent employs composite material structures where a low-CTE dielectric layer is combined with conductive traces and bonding interfaces. The dielectric layer serves as a thermal expansion buffer that protects the bonding interfaces from stress, while the conductive traces provide electrical connectivity. This composite approach maintains manufacturing feasibility while solving the thermal mismatch problem.
2Productivity
If interposers are designed with finer pitch connections to improve connectivity, then electrical connection density increases, but manufacturing precision requirements and alignment difficulty increase
Solution Approach 1:
The patent uses redistribution layers that can route signals in multiple dimensions and planes within the interposer structure. This allows the interposer to accept fine-pitch connections from the semiconductor chip on one side and transform them into coarser-pitch connections on the PCB side, effectively decoupling the alignment requirements of the two interfaces and enabling high connection density without proportionally increasing manufacturing precision requirements.
3Reliability
If thermal expansion mismatch is not addressed, then material selection is easier and cost is lower, but thermal stress causes delamination and cracking
Solution Approach 1:
The patent fundamentally changes the thermal expansion parameter of the dielectric material by selecting materials with CTE less than 8 ppm/°C (such as ceramic substrates like alumina, aluminum nitride, or silicon carbide) to match the CTE of semiconductor chips and PCBs. This parameter change resolves the thermal expansion mismatch problem that causes delamination and cracking at bonding interfaces, thereby improving reliability without significantly complicating the manufacturing process.
Solution Approach 2:
The low-CTE dielectric layer acts as a preventive cushion that protects the bonding interfaces from thermal stress before damage occurs. By selecting materials with matched thermal expansion properties, the interposer preemptively compensates for thermal expansion differences between the semiconductor chip and PCB, preventing delamination and cracking during temperature cycling in the service environment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances bonding reliability by reducing thermal stress, allowing for finer pitch connections and improved durability by matching thermal expansion, and enabling efficient electrical connections between microelectronic elements and circuit panels.
Implementation Method 1
The dielectric layer material has a coefficient of thermal expansion of less than 8 parts per million per degree Celsius (ppm/°C.)
Data Source
AI summary
A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.