Low CTE Layer for GaN on Silicon Wafer Distortion
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Solution Overview
Problem
Existing methods for forming III-V family layers on silicon substrates often result in wafer bending or distortion due to drastic temperature changes, leading to wafer defects and reduced yield and device performance.
Innovation Solution
A method involving the formation of a low coefficient-of-thermal-expansion (CTE) layer on a silicon substrate, bonding it to another silicon substrate, thinning, and growing a gallium nitride layer using an epitaxial process, with stress balancing to prevent distortion, including the use of silicon oxide as the low CTE layer and hydrogen implantation for stress management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a III-V family layer is formed on a silicon substrate using existing methods, then cost is reduced compared to sapphire substrates, but wafer distortion occurs due to thermal expansion mismatch during temperature changes
Solution Approach 1:
An intermediate layer is introduced between the silicon substrate and the III-V family layer. This intermediate layer has thermal expansion properties that bridge the mismatch between silicon and III-V materials, preventing wafer distortion during temperature changes while allowing the cost-effective silicon substrate to be used
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different material properties. The combination of silicon substrate, intermediate layer, and III-V family layer creates a composite system that balances thermal expansion characteristics, maintaining wafer flatness while reducing overall cost compared to pure sapphire substrates
2Productivity
If drastic temperature changes are applied during fabrication, then the epitaxial growth process can be completed, but wafer bending and distortion occur
Solution Approach 1:
The patent modifies the thermal parameters of the fabrication process by introducing an intermediate layer that changes the overall thermal expansion behavior of the wafer stack. This allows the epitaxial growth to proceed with temperature changes while the intermediate layer compensates for differential expansion, preventing wafer bending
3Manufacturing precision
If a low CTE layer is added to prevent distortion, then wafer flatness is maintained, but process complexity increases
Solution Approach 1:
The intermediate layer is applied selectively to specific regions or the entire substrate surface in a controlled manner. This localized approach maintains wafer flatness where needed while keeping the overall process complexity manageable by focusing the additional step where it provides maximum benefit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents wafer distortion during gallium nitride growth on silicon substrates, reducing defects and maintaining device flatness, while being cost-effective and compatible with existing fabrication processes.
Implementation Method 1
a first layer having a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon... The low CTE layer has a CTE less than a CTE of silicon
Implementation Method 2
hydrogen implantation for stress management
Data Source
AI summary
Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.